/*==============================================================================
 Copyright (c) 2015-2018 Qualcomm Technologies, Inc.
 All Rights Reserved.
 Confidential and Proprietary - Qualcomm Technologies, Inc.
==============================================================================*/
#ifndef TITAN170_ICP_H
#define TITAN170_ICP_H

/*----------------------------------------------------------------------
        Offset and Mask
----------------------------------------------------------------------*/

#define ICP_REGS_FIRST 0x0 

#define ICP_REGS_LAST 0x18200 

#define ICP_REGS_COUNT 0xec 

#define regICP_ICP_QGIC2_GICD_CTLR 0x0  /*register offset*/
#define ICP_ICP_QGIC2_GICD_CTLR_ENABLE_MASK 0x1
#define ICP_ICP_QGIC2_GICD_CTLR_ENABLE_SHIFT 0x0
#define ICP_ICP_QGIC2_GICD_CTLR_ENABLE_NS_MASK 0x2
#define ICP_ICP_QGIC2_GICD_CTLR_ENABLE_NS_SHIFT 0x1
#define ICP_ICP_QGIC2_GICD_CTLR_UNUSED0_MASK 0xfffffffc
#define ICP_ICP_QGIC2_GICD_CTLR_UNUSED0_SHIFT 0x2

#define regICP_ICP_QGIC2_GICD_TYPER 0x4  /*register offset*/
#define ICP_ICP_QGIC2_GICD_TYPER_IT_LINES_MASK 0x1f
#define ICP_ICP_QGIC2_GICD_TYPER_IT_LINES_SHIFT 0x0
#define ICP_ICP_QGIC2_GICD_TYPER_CPU_NUM_MASK 0xe0
#define ICP_ICP_QGIC2_GICD_TYPER_CPU_NUM_SHIFT 0x5
#define ICP_ICP_QGIC2_GICD_TYPER_UNUSED0_MASK 0x300
#define ICP_ICP_QGIC2_GICD_TYPER_UNUSED0_SHIFT 0x8
#define ICP_ICP_QGIC2_GICD_TYPER_TZ_MASK 0x400
#define ICP_ICP_QGIC2_GICD_TYPER_TZ_SHIFT 0xa
#define ICP_ICP_QGIC2_GICD_TYPER_LSPI_MASK 0xf800
#define ICP_ICP_QGIC2_GICD_TYPER_LSPI_SHIFT 0xb
#define ICP_ICP_QGIC2_GICD_TYPER_UNUSED1_MASK 0xffff0000
#define ICP_ICP_QGIC2_GICD_TYPER_UNUSED1_SHIFT 0x10

#define regICP_ICP_QGIC2_GICD_IIDR 0x8  /*register offset*/
#define ICP_ICP_QGIC2_GICD_IIDR_IMPLEMENTOR_MASK 0xfff
#define ICP_ICP_QGIC2_GICD_IIDR_IMPLEMENTOR_SHIFT 0x0
#define ICP_ICP_QGIC2_GICD_IIDR_REVISION_MASK 0xf000
#define ICP_ICP_QGIC2_GICD_IIDR_REVISION_SHIFT 0xc
#define ICP_ICP_QGIC2_GICD_IIDR_UNUSED0_MASK 0xffff0000
#define ICP_ICP_QGIC2_GICD_IIDR_UNUSED0_SHIFT 0x10

#define regICP_ICP_QGIC2_GICD_ANSACR 0x20  /*register offset*/
#define ICP_ICP_QGIC2_GICD_ANSACR_GICD_CGCR_MASK 0x1
#define ICP_ICP_QGIC2_GICD_ANSACR_GICD_CGCR_SHIFT 0x0
#define ICP_ICP_QGIC2_GICD_ANSACR_UNUSED0_MASK 0xfffffffe
#define ICP_ICP_QGIC2_GICD_ANSACR_UNUSED0_SHIFT 0x1

#define regICP_ICP_QGIC2_GICD_CGCR 0x24  /*register offset*/
#define ICP_ICP_QGIC2_GICD_CGCR_DI_RD_MASK 0x1
#define ICP_ICP_QGIC2_GICD_CGCR_DI_RD_SHIFT 0x0
#define ICP_ICP_QGIC2_GICD_CGCR_DI_DEMET_MASK 0x2
#define ICP_ICP_QGIC2_GICD_CGCR_DI_DEMET_SHIFT 0x1
#define ICP_ICP_QGIC2_GICD_CGCR_DI_PPI_SPI_STATE_MASK 0x4
#define ICP_ICP_QGIC2_GICD_CGCR_DI_PPI_SPI_STATE_SHIFT 0x2
#define ICP_ICP_QGIC2_GICD_CGCR_DI_SGI_STATE_MASK 0x8
#define ICP_ICP_QGIC2_GICD_CGCR_DI_SGI_STATE_SHIFT 0x3
#define ICP_ICP_QGIC2_GICD_CGCR_UNUSED0_MASK 0xfff0
#define ICP_ICP_QGIC2_GICD_CGCR_UNUSED0_SHIFT 0x4
#define ICP_ICP_QGIC2_GICD_CGCR_TOP_MASK 0x10000
#define ICP_ICP_QGIC2_GICD_CGCR_TOP_SHIFT 0x10
#define ICP_ICP_QGIC2_GICD_CGCR_UNUSED1_MASK 0xfffe0000
#define ICP_ICP_QGIC2_GICD_CGCR_UNUSED1_SHIFT 0x11

#define regICP_ICP_QGIC2_GICD_HW_VERSION 0x30  /*register offset*/
#define ICP_ICP_QGIC2_GICD_HW_VERSION_STEP_MASK 0xffff
#define ICP_ICP_QGIC2_GICD_HW_VERSION_STEP_SHIFT 0x0
#define ICP_ICP_QGIC2_GICD_HW_VERSION_MINOR_MASK 0xfff0000
#define ICP_ICP_QGIC2_GICD_HW_VERSION_MINOR_SHIFT 0x10
#define ICP_ICP_QGIC2_GICD_HW_VERSION_MAJOR_MASK 0xf0000000
#define ICP_ICP_QGIC2_GICD_HW_VERSION_MAJOR_SHIFT 0x1c

#define regICP_ICP_QGIC2_GICD_ISR0 0x80  /*register offset*/
#define ICP_ICP_QGIC2_GICD_ISR0_INT_NS_MASK 0xffffffff
#define ICP_ICP_QGIC2_GICD_ISR0_INT_NS_SHIFT 0x0

#define regICP_ICP_QGIC2_GICD_ISR1 0x84  /*register offset*/
#define ICP_ICP_QGIC2_GICD_ISR1_INT_NS_MASK 0xffffffff
#define ICP_ICP_QGIC2_GICD_ISR1_INT_NS_SHIFT 0x0

#define regICP_ICP_QGIC2_GICD_ISR2 0x88  /*register offset*/
#define ICP_ICP_QGIC2_GICD_ISR2_INT_NS_MASK 0xffffffff
#define ICP_ICP_QGIC2_GICD_ISR2_INT_NS_SHIFT 0x0

#define regICP_ICP_QGIC2_GICD_ISENABLER0 0x100  /*register offset*/
#define ICP_ICP_QGIC2_GICD_ISENABLER0_INT_MASK 0xffffffff
#define ICP_ICP_QGIC2_GICD_ISENABLER0_INT_SHIFT 0x0

#define regICP_ICP_QGIC2_GICD_ISENABLER1 0x104  /*register offset*/
#define ICP_ICP_QGIC2_GICD_ISENABLER1_INT_MASK 0xffffffff
#define ICP_ICP_QGIC2_GICD_ISENABLER1_INT_SHIFT 0x0

#define regICP_ICP_QGIC2_GICD_ISENABLER2 0x108  /*register offset*/
#define ICP_ICP_QGIC2_GICD_ISENABLER2_INT_MASK 0xffffffff
#define ICP_ICP_QGIC2_GICD_ISENABLER2_INT_SHIFT 0x0

#define regICP_ICP_QGIC2_GICD_ICENABLER0 0x180  /*register offset*/
#define ICP_ICP_QGIC2_GICD_ICENABLER0_INT_MASK 0xffffffff
#define ICP_ICP_QGIC2_GICD_ICENABLER0_INT_SHIFT 0x0

#define regICP_ICP_QGIC2_GICD_ICENABLER1 0x184  /*register offset*/
#define ICP_ICP_QGIC2_GICD_ICENABLER1_INT_MASK 0xffffffff
#define ICP_ICP_QGIC2_GICD_ICENABLER1_INT_SHIFT 0x0

#define regICP_ICP_QGIC2_GICD_ICENABLER2 0x188  /*register offset*/
#define ICP_ICP_QGIC2_GICD_ICENABLER2_INT_MASK 0xffffffff
#define ICP_ICP_QGIC2_GICD_ICENABLER2_INT_SHIFT 0x0

#define regICP_ICP_QGIC2_GICD_ISPENDR0 0x200  /*register offset*/
#define ICP_ICP_QGIC2_GICD_ISPENDR0_INT_MASK 0xffffffff
#define ICP_ICP_QGIC2_GICD_ISPENDR0_INT_SHIFT 0x0

#define regICP_ICP_QGIC2_GICD_ISPENDR1 0x204  /*register offset*/
#define ICP_ICP_QGIC2_GICD_ISPENDR1_INT_MASK 0xffffffff
#define ICP_ICP_QGIC2_GICD_ISPENDR1_INT_SHIFT 0x0

#define regICP_ICP_QGIC2_GICD_ISPENDR2 0x208  /*register offset*/
#define ICP_ICP_QGIC2_GICD_ISPENDR2_INT_MASK 0xffffffff
#define ICP_ICP_QGIC2_GICD_ISPENDR2_INT_SHIFT 0x0

#define regICP_ICP_QGIC2_GICD_ICPENDR0 0x280  /*register offset*/
#define ICP_ICP_QGIC2_GICD_ICPENDR0_INT_MASK 0xffffffff
#define ICP_ICP_QGIC2_GICD_ICPENDR0_INT_SHIFT 0x0

#define regICP_ICP_QGIC2_GICD_ICPENDR1 0x284  /*register offset*/
#define ICP_ICP_QGIC2_GICD_ICPENDR1_INT_MASK 0xffffffff
#define ICP_ICP_QGIC2_GICD_ICPENDR1_INT_SHIFT 0x0

#define regICP_ICP_QGIC2_GICD_ICPENDR2 0x288  /*register offset*/
#define ICP_ICP_QGIC2_GICD_ICPENDR2_INT_MASK 0xffffffff
#define ICP_ICP_QGIC2_GICD_ICPENDR2_INT_SHIFT 0x0

#define regICP_ICP_QGIC2_GICD_ISACTIVER0 0x300  /*register offset*/
#define ICP_ICP_QGIC2_GICD_ISACTIVER0_INT_MASK 0xffffffff
#define ICP_ICP_QGIC2_GICD_ISACTIVER0_INT_SHIFT 0x0

#define regICP_ICP_QGIC2_GICD_ISACTIVER1 0x304  /*register offset*/
#define ICP_ICP_QGIC2_GICD_ISACTIVER1_INT_MASK 0xffffffff
#define ICP_ICP_QGIC2_GICD_ISACTIVER1_INT_SHIFT 0x0

#define regICP_ICP_QGIC2_GICD_ISACTIVER2 0x308  /*register offset*/
#define ICP_ICP_QGIC2_GICD_ISACTIVER2_INT_MASK 0xffffffff
#define ICP_ICP_QGIC2_GICD_ISACTIVER2_INT_SHIFT 0x0

#define regICP_ICP_QGIC2_GICD_ICACTIVER0 0x380  /*register offset*/
#define ICP_ICP_QGIC2_GICD_ICACTIVER0_INT_MASK 0xffffffff
#define ICP_ICP_QGIC2_GICD_ICACTIVER0_INT_SHIFT 0x0

#define regICP_ICP_QGIC2_GICD_ICACTIVER1 0x384  /*register offset*/
#define ICP_ICP_QGIC2_GICD_ICACTIVER1_INT_MASK 0xffffffff
#define ICP_ICP_QGIC2_GICD_ICACTIVER1_INT_SHIFT 0x0

#define regICP_ICP_QGIC2_GICD_ICACTIVER2 0x388  /*register offset*/
#define ICP_ICP_QGIC2_GICD_ICACTIVER2_INT_MASK 0xffffffff
#define ICP_ICP_QGIC2_GICD_ICACTIVER2_INT_SHIFT 0x0

#define regICP_ICP_QGIC2_GICD_IPRIORITYR0 0x400  /*register offset*/
#define ICP_ICP_QGIC2_GICD_IPRIORITYR0_UNUSED0_MASK 0x7
#define ICP_ICP_QGIC2_GICD_IPRIORITYR0_UNUSED0_SHIFT 0x0
#define ICP_ICP_QGIC2_GICD_IPRIORITYR0_INT0_MASK 0xf8
#define ICP_ICP_QGIC2_GICD_IPRIORITYR0_INT0_SHIFT 0x3
#define ICP_ICP_QGIC2_GICD_IPRIORITYR0_UNUSED1_MASK 0x700
#define ICP_ICP_QGIC2_GICD_IPRIORITYR0_UNUSED1_SHIFT 0x8
#define ICP_ICP_QGIC2_GICD_IPRIORITYR0_INT1_MASK 0xf800
#define ICP_ICP_QGIC2_GICD_IPRIORITYR0_INT1_SHIFT 0xb
#define ICP_ICP_QGIC2_GICD_IPRIORITYR0_UNUSED2_MASK 0x70000
#define ICP_ICP_QGIC2_GICD_IPRIORITYR0_UNUSED2_SHIFT 0x10
#define ICP_ICP_QGIC2_GICD_IPRIORITYR0_INT2_MASK 0xf80000
#define ICP_ICP_QGIC2_GICD_IPRIORITYR0_INT2_SHIFT 0x13
#define ICP_ICP_QGIC2_GICD_IPRIORITYR0_UNUSED3_MASK 0x7000000
#define ICP_ICP_QGIC2_GICD_IPRIORITYR0_UNUSED3_SHIFT 0x18
#define ICP_ICP_QGIC2_GICD_IPRIORITYR0_INT3_MASK 0xf8000000
#define ICP_ICP_QGIC2_GICD_IPRIORITYR0_INT3_SHIFT 0x1b

#define regICP_ICP_QGIC2_GICD_IPRIORITYR1 0x404  /*register offset*/
#define ICP_ICP_QGIC2_GICD_IPRIORITYR1_UNUSED0_MASK 0x7
#define ICP_ICP_QGIC2_GICD_IPRIORITYR1_UNUSED0_SHIFT 0x0
#define ICP_ICP_QGIC2_GICD_IPRIORITYR1_INT0_MASK 0xf8
#define ICP_ICP_QGIC2_GICD_IPRIORITYR1_INT0_SHIFT 0x3
#define ICP_ICP_QGIC2_GICD_IPRIORITYR1_UNUSED1_MASK 0x700
#define ICP_ICP_QGIC2_GICD_IPRIORITYR1_UNUSED1_SHIFT 0x8
#define ICP_ICP_QGIC2_GICD_IPRIORITYR1_INT1_MASK 0xf800
#define ICP_ICP_QGIC2_GICD_IPRIORITYR1_INT1_SHIFT 0xb
#define ICP_ICP_QGIC2_GICD_IPRIORITYR1_UNUSED2_MASK 0x70000
#define ICP_ICP_QGIC2_GICD_IPRIORITYR1_UNUSED2_SHIFT 0x10
#define ICP_ICP_QGIC2_GICD_IPRIORITYR1_INT2_MASK 0xf80000
#define ICP_ICP_QGIC2_GICD_IPRIORITYR1_INT2_SHIFT 0x13
#define ICP_ICP_QGIC2_GICD_IPRIORITYR1_UNUSED3_MASK 0x7000000
#define ICP_ICP_QGIC2_GICD_IPRIORITYR1_UNUSED3_SHIFT 0x18
#define ICP_ICP_QGIC2_GICD_IPRIORITYR1_INT3_MASK 0xf8000000
#define ICP_ICP_QGIC2_GICD_IPRIORITYR1_INT3_SHIFT 0x1b

#define regICP_ICP_QGIC2_GICD_IPRIORITYR2 0x408  /*register offset*/
#define ICP_ICP_QGIC2_GICD_IPRIORITYR2_UNUSED0_MASK 0x7
#define ICP_ICP_QGIC2_GICD_IPRIORITYR2_UNUSED0_SHIFT 0x0
#define ICP_ICP_QGIC2_GICD_IPRIORITYR2_INT0_MASK 0xf8
#define ICP_ICP_QGIC2_GICD_IPRIORITYR2_INT0_SHIFT 0x3
#define ICP_ICP_QGIC2_GICD_IPRIORITYR2_UNUSED1_MASK 0x700
#define ICP_ICP_QGIC2_GICD_IPRIORITYR2_UNUSED1_SHIFT 0x8
#define ICP_ICP_QGIC2_GICD_IPRIORITYR2_INT1_MASK 0xf800
#define ICP_ICP_QGIC2_GICD_IPRIORITYR2_INT1_SHIFT 0xb
#define ICP_ICP_QGIC2_GICD_IPRIORITYR2_UNUSED2_MASK 0x70000
#define ICP_ICP_QGIC2_GICD_IPRIORITYR2_UNUSED2_SHIFT 0x10
#define ICP_ICP_QGIC2_GICD_IPRIORITYR2_INT2_MASK 0xf80000
#define ICP_ICP_QGIC2_GICD_IPRIORITYR2_INT2_SHIFT 0x13
#define ICP_ICP_QGIC2_GICD_IPRIORITYR2_UNUSED3_MASK 0x7000000
#define ICP_ICP_QGIC2_GICD_IPRIORITYR2_UNUSED3_SHIFT 0x18
#define ICP_ICP_QGIC2_GICD_IPRIORITYR2_INT3_MASK 0xf8000000
#define ICP_ICP_QGIC2_GICD_IPRIORITYR2_INT3_SHIFT 0x1b

#define regICP_ICP_QGIC2_GICD_IPRIORITYR3 0x40c  /*register offset*/
#define ICP_ICP_QGIC2_GICD_IPRIORITYR3_UNUSED0_MASK 0x7
#define ICP_ICP_QGIC2_GICD_IPRIORITYR3_UNUSED0_SHIFT 0x0
#define ICP_ICP_QGIC2_GICD_IPRIORITYR3_INT0_MASK 0xf8
#define ICP_ICP_QGIC2_GICD_IPRIORITYR3_INT0_SHIFT 0x3
#define ICP_ICP_QGIC2_GICD_IPRIORITYR3_UNUSED1_MASK 0x700
#define ICP_ICP_QGIC2_GICD_IPRIORITYR3_UNUSED1_SHIFT 0x8
#define ICP_ICP_QGIC2_GICD_IPRIORITYR3_INT1_MASK 0xf800
#define ICP_ICP_QGIC2_GICD_IPRIORITYR3_INT1_SHIFT 0xb
#define ICP_ICP_QGIC2_GICD_IPRIORITYR3_UNUSED2_MASK 0x70000
#define ICP_ICP_QGIC2_GICD_IPRIORITYR3_UNUSED2_SHIFT 0x10
#define ICP_ICP_QGIC2_GICD_IPRIORITYR3_INT2_MASK 0xf80000
#define ICP_ICP_QGIC2_GICD_IPRIORITYR3_INT2_SHIFT 0x13
#define ICP_ICP_QGIC2_GICD_IPRIORITYR3_UNUSED3_MASK 0x7000000
#define ICP_ICP_QGIC2_GICD_IPRIORITYR3_UNUSED3_SHIFT 0x18
#define ICP_ICP_QGIC2_GICD_IPRIORITYR3_INT3_MASK 0xf8000000
#define ICP_ICP_QGIC2_GICD_IPRIORITYR3_INT3_SHIFT 0x1b

#define regICP_ICP_QGIC2_GICD_IPRIORITYR4 0x410  /*register offset*/
#define ICP_ICP_QGIC2_GICD_IPRIORITYR4_UNUSED0_MASK 0x7
#define ICP_ICP_QGIC2_GICD_IPRIORITYR4_UNUSED0_SHIFT 0x0
#define ICP_ICP_QGIC2_GICD_IPRIORITYR4_INT0_MASK 0xf8
#define ICP_ICP_QGIC2_GICD_IPRIORITYR4_INT0_SHIFT 0x3
#define ICP_ICP_QGIC2_GICD_IPRIORITYR4_UNUSED1_MASK 0x700
#define ICP_ICP_QGIC2_GICD_IPRIORITYR4_UNUSED1_SHIFT 0x8
#define ICP_ICP_QGIC2_GICD_IPRIORITYR4_INT1_MASK 0xf800
#define ICP_ICP_QGIC2_GICD_IPRIORITYR4_INT1_SHIFT 0xb
#define ICP_ICP_QGIC2_GICD_IPRIORITYR4_UNUSED2_MASK 0x70000
#define ICP_ICP_QGIC2_GICD_IPRIORITYR4_UNUSED2_SHIFT 0x10
#define ICP_ICP_QGIC2_GICD_IPRIORITYR4_INT2_MASK 0xf80000
#define ICP_ICP_QGIC2_GICD_IPRIORITYR4_INT2_SHIFT 0x13
#define ICP_ICP_QGIC2_GICD_IPRIORITYR4_UNUSED3_MASK 0x7000000
#define ICP_ICP_QGIC2_GICD_IPRIORITYR4_UNUSED3_SHIFT 0x18
#define ICP_ICP_QGIC2_GICD_IPRIORITYR4_INT3_MASK 0xf8000000
#define ICP_ICP_QGIC2_GICD_IPRIORITYR4_INT3_SHIFT 0x1b

#define regICP_ICP_QGIC2_GICD_IPRIORITYR5 0x414  /*register offset*/
#define ICP_ICP_QGIC2_GICD_IPRIORITYR5_UNUSED0_MASK 0x7
#define ICP_ICP_QGIC2_GICD_IPRIORITYR5_UNUSED0_SHIFT 0x0
#define ICP_ICP_QGIC2_GICD_IPRIORITYR5_INT0_MASK 0xf8
#define ICP_ICP_QGIC2_GICD_IPRIORITYR5_INT0_SHIFT 0x3
#define ICP_ICP_QGIC2_GICD_IPRIORITYR5_UNUSED1_MASK 0x700
#define ICP_ICP_QGIC2_GICD_IPRIORITYR5_UNUSED1_SHIFT 0x8
#define ICP_ICP_QGIC2_GICD_IPRIORITYR5_INT1_MASK 0xf800
#define ICP_ICP_QGIC2_GICD_IPRIORITYR5_INT1_SHIFT 0xb
#define ICP_ICP_QGIC2_GICD_IPRIORITYR5_UNUSED2_MASK 0x70000
#define ICP_ICP_QGIC2_GICD_IPRIORITYR5_UNUSED2_SHIFT 0x10
#define ICP_ICP_QGIC2_GICD_IPRIORITYR5_INT2_MASK 0xf80000
#define ICP_ICP_QGIC2_GICD_IPRIORITYR5_INT2_SHIFT 0x13
#define ICP_ICP_QGIC2_GICD_IPRIORITYR5_UNUSED3_MASK 0x7000000
#define ICP_ICP_QGIC2_GICD_IPRIORITYR5_UNUSED3_SHIFT 0x18
#define ICP_ICP_QGIC2_GICD_IPRIORITYR5_INT3_MASK 0xf8000000
#define ICP_ICP_QGIC2_GICD_IPRIORITYR5_INT3_SHIFT 0x1b

#define regICP_ICP_QGIC2_GICD_IPRIORITYR6 0x418  /*register offset*/
#define ICP_ICP_QGIC2_GICD_IPRIORITYR6_UNUSED0_MASK 0x7
#define ICP_ICP_QGIC2_GICD_IPRIORITYR6_UNUSED0_SHIFT 0x0
#define ICP_ICP_QGIC2_GICD_IPRIORITYR6_INT0_MASK 0xf8
#define ICP_ICP_QGIC2_GICD_IPRIORITYR6_INT0_SHIFT 0x3
#define ICP_ICP_QGIC2_GICD_IPRIORITYR6_UNUSED1_MASK 0x700
#define ICP_ICP_QGIC2_GICD_IPRIORITYR6_UNUSED1_SHIFT 0x8
#define ICP_ICP_QGIC2_GICD_IPRIORITYR6_INT1_MASK 0xf800
#define ICP_ICP_QGIC2_GICD_IPRIORITYR6_INT1_SHIFT 0xb
#define ICP_ICP_QGIC2_GICD_IPRIORITYR6_UNUSED2_MASK 0x70000
#define ICP_ICP_QGIC2_GICD_IPRIORITYR6_UNUSED2_SHIFT 0x10
#define ICP_ICP_QGIC2_GICD_IPRIORITYR6_INT2_MASK 0xf80000
#define ICP_ICP_QGIC2_GICD_IPRIORITYR6_INT2_SHIFT 0x13
#define ICP_ICP_QGIC2_GICD_IPRIORITYR6_UNUSED3_MASK 0x7000000
#define ICP_ICP_QGIC2_GICD_IPRIORITYR6_UNUSED3_SHIFT 0x18
#define ICP_ICP_QGIC2_GICD_IPRIORITYR6_INT3_MASK 0xf8000000
#define ICP_ICP_QGIC2_GICD_IPRIORITYR6_INT3_SHIFT 0x1b

#define regICP_ICP_QGIC2_GICD_IPRIORITYR7 0x41c  /*register offset*/
#define ICP_ICP_QGIC2_GICD_IPRIORITYR7_UNUSED0_MASK 0x7
#define ICP_ICP_QGIC2_GICD_IPRIORITYR7_UNUSED0_SHIFT 0x0
#define ICP_ICP_QGIC2_GICD_IPRIORITYR7_INT0_MASK 0xf8
#define ICP_ICP_QGIC2_GICD_IPRIORITYR7_INT0_SHIFT 0x3
#define ICP_ICP_QGIC2_GICD_IPRIORITYR7_UNUSED1_MASK 0x700
#define ICP_ICP_QGIC2_GICD_IPRIORITYR7_UNUSED1_SHIFT 0x8
#define ICP_ICP_QGIC2_GICD_IPRIORITYR7_INT1_MASK 0xf800
#define ICP_ICP_QGIC2_GICD_IPRIORITYR7_INT1_SHIFT 0xb
#define ICP_ICP_QGIC2_GICD_IPRIORITYR7_UNUSED2_MASK 0x70000
#define ICP_ICP_QGIC2_GICD_IPRIORITYR7_UNUSED2_SHIFT 0x10
#define ICP_ICP_QGIC2_GICD_IPRIORITYR7_INT2_MASK 0xf80000
#define ICP_ICP_QGIC2_GICD_IPRIORITYR7_INT2_SHIFT 0x13
#define ICP_ICP_QGIC2_GICD_IPRIORITYR7_UNUSED3_MASK 0x7000000
#define ICP_ICP_QGIC2_GICD_IPRIORITYR7_UNUSED3_SHIFT 0x18
#define ICP_ICP_QGIC2_GICD_IPRIORITYR7_INT3_MASK 0xf8000000
#define ICP_ICP_QGIC2_GICD_IPRIORITYR7_INT3_SHIFT 0x1b

#define regICP_ICP_QGIC2_GICD_IPRIORITYR8 0x420  /*register offset*/
#define ICP_ICP_QGIC2_GICD_IPRIORITYR8_UNUSED0_MASK 0x7
#define ICP_ICP_QGIC2_GICD_IPRIORITYR8_UNUSED0_SHIFT 0x0
#define ICP_ICP_QGIC2_GICD_IPRIORITYR8_INT0_MASK 0xf8
#define ICP_ICP_QGIC2_GICD_IPRIORITYR8_INT0_SHIFT 0x3
#define ICP_ICP_QGIC2_GICD_IPRIORITYR8_UNUSED1_MASK 0x700
#define ICP_ICP_QGIC2_GICD_IPRIORITYR8_UNUSED1_SHIFT 0x8
#define ICP_ICP_QGIC2_GICD_IPRIORITYR8_INT1_MASK 0xf800
#define ICP_ICP_QGIC2_GICD_IPRIORITYR8_INT1_SHIFT 0xb
#define ICP_ICP_QGIC2_GICD_IPRIORITYR8_UNUSED2_MASK 0x70000
#define ICP_ICP_QGIC2_GICD_IPRIORITYR8_UNUSED2_SHIFT 0x10
#define ICP_ICP_QGIC2_GICD_IPRIORITYR8_INT2_MASK 0xf80000
#define ICP_ICP_QGIC2_GICD_IPRIORITYR8_INT2_SHIFT 0x13
#define ICP_ICP_QGIC2_GICD_IPRIORITYR8_UNUSED3_MASK 0x7000000
#define ICP_ICP_QGIC2_GICD_IPRIORITYR8_UNUSED3_SHIFT 0x18
#define ICP_ICP_QGIC2_GICD_IPRIORITYR8_INT3_MASK 0xf8000000
#define ICP_ICP_QGIC2_GICD_IPRIORITYR8_INT3_SHIFT 0x1b

#define regICP_ICP_QGIC2_GICD_IPRIORITYR9 0x424  /*register offset*/
#define ICP_ICP_QGIC2_GICD_IPRIORITYR9_UNUSED0_MASK 0x7
#define ICP_ICP_QGIC2_GICD_IPRIORITYR9_UNUSED0_SHIFT 0x0
#define ICP_ICP_QGIC2_GICD_IPRIORITYR9_INT0_MASK 0xf8
#define ICP_ICP_QGIC2_GICD_IPRIORITYR9_INT0_SHIFT 0x3
#define ICP_ICP_QGIC2_GICD_IPRIORITYR9_UNUSED1_MASK 0x700
#define ICP_ICP_QGIC2_GICD_IPRIORITYR9_UNUSED1_SHIFT 0x8
#define ICP_ICP_QGIC2_GICD_IPRIORITYR9_INT1_MASK 0xf800
#define ICP_ICP_QGIC2_GICD_IPRIORITYR9_INT1_SHIFT 0xb
#define ICP_ICP_QGIC2_GICD_IPRIORITYR9_UNUSED2_MASK 0x70000
#define ICP_ICP_QGIC2_GICD_IPRIORITYR9_UNUSED2_SHIFT 0x10
#define ICP_ICP_QGIC2_GICD_IPRIORITYR9_INT2_MASK 0xf80000
#define ICP_ICP_QGIC2_GICD_IPRIORITYR9_INT2_SHIFT 0x13
#define ICP_ICP_QGIC2_GICD_IPRIORITYR9_UNUSED3_MASK 0x7000000
#define ICP_ICP_QGIC2_GICD_IPRIORITYR9_UNUSED3_SHIFT 0x18
#define ICP_ICP_QGIC2_GICD_IPRIORITYR9_INT3_MASK 0xf8000000
#define ICP_ICP_QGIC2_GICD_IPRIORITYR9_INT3_SHIFT 0x1b

#define regICP_ICP_QGIC2_GICD_IPRIORITYR10 0x428  /*register offset*/
#define ICP_ICP_QGIC2_GICD_IPRIORITYR10_UNUSED0_MASK 0x7
#define ICP_ICP_QGIC2_GICD_IPRIORITYR10_UNUSED0_SHIFT 0x0
#define ICP_ICP_QGIC2_GICD_IPRIORITYR10_INT0_MASK 0xf8
#define ICP_ICP_QGIC2_GICD_IPRIORITYR10_INT0_SHIFT 0x3
#define ICP_ICP_QGIC2_GICD_IPRIORITYR10_UNUSED1_MASK 0x700
#define ICP_ICP_QGIC2_GICD_IPRIORITYR10_UNUSED1_SHIFT 0x8
#define ICP_ICP_QGIC2_GICD_IPRIORITYR10_INT1_MASK 0xf800
#define ICP_ICP_QGIC2_GICD_IPRIORITYR10_INT1_SHIFT 0xb
#define ICP_ICP_QGIC2_GICD_IPRIORITYR10_UNUSED2_MASK 0x70000
#define ICP_ICP_QGIC2_GICD_IPRIORITYR10_UNUSED2_SHIFT 0x10
#define ICP_ICP_QGIC2_GICD_IPRIORITYR10_INT2_MASK 0xf80000
#define ICP_ICP_QGIC2_GICD_IPRIORITYR10_INT2_SHIFT 0x13
#define ICP_ICP_QGIC2_GICD_IPRIORITYR10_UNUSED3_MASK 0x7000000
#define ICP_ICP_QGIC2_GICD_IPRIORITYR10_UNUSED3_SHIFT 0x18
#define ICP_ICP_QGIC2_GICD_IPRIORITYR10_INT3_MASK 0xf8000000
#define ICP_ICP_QGIC2_GICD_IPRIORITYR10_INT3_SHIFT 0x1b

#define regICP_ICP_QGIC2_GICD_IPRIORITYR11 0x42c  /*register offset*/
#define ICP_ICP_QGIC2_GICD_IPRIORITYR11_UNUSED0_MASK 0x7
#define ICP_ICP_QGIC2_GICD_IPRIORITYR11_UNUSED0_SHIFT 0x0
#define ICP_ICP_QGIC2_GICD_IPRIORITYR11_INT0_MASK 0xf8
#define ICP_ICP_QGIC2_GICD_IPRIORITYR11_INT0_SHIFT 0x3
#define ICP_ICP_QGIC2_GICD_IPRIORITYR11_UNUSED1_MASK 0x700
#define ICP_ICP_QGIC2_GICD_IPRIORITYR11_UNUSED1_SHIFT 0x8
#define ICP_ICP_QGIC2_GICD_IPRIORITYR11_INT1_MASK 0xf800
#define ICP_ICP_QGIC2_GICD_IPRIORITYR11_INT1_SHIFT 0xb
#define ICP_ICP_QGIC2_GICD_IPRIORITYR11_UNUSED2_MASK 0x70000
#define ICP_ICP_QGIC2_GICD_IPRIORITYR11_UNUSED2_SHIFT 0x10
#define ICP_ICP_QGIC2_GICD_IPRIORITYR11_INT2_MASK 0xf80000
#define ICP_ICP_QGIC2_GICD_IPRIORITYR11_INT2_SHIFT 0x13
#define ICP_ICP_QGIC2_GICD_IPRIORITYR11_UNUSED3_MASK 0x7000000
#define ICP_ICP_QGIC2_GICD_IPRIORITYR11_UNUSED3_SHIFT 0x18
#define ICP_ICP_QGIC2_GICD_IPRIORITYR11_INT3_MASK 0xf8000000
#define ICP_ICP_QGIC2_GICD_IPRIORITYR11_INT3_SHIFT 0x1b

#define regICP_ICP_QGIC2_GICD_IPRIORITYR12 0x430  /*register offset*/
#define ICP_ICP_QGIC2_GICD_IPRIORITYR12_UNUSED0_MASK 0x7
#define ICP_ICP_QGIC2_GICD_IPRIORITYR12_UNUSED0_SHIFT 0x0
#define ICP_ICP_QGIC2_GICD_IPRIORITYR12_INT0_MASK 0xf8
#define ICP_ICP_QGIC2_GICD_IPRIORITYR12_INT0_SHIFT 0x3
#define ICP_ICP_QGIC2_GICD_IPRIORITYR12_UNUSED1_MASK 0x700
#define ICP_ICP_QGIC2_GICD_IPRIORITYR12_UNUSED1_SHIFT 0x8
#define ICP_ICP_QGIC2_GICD_IPRIORITYR12_INT1_MASK 0xf800
#define ICP_ICP_QGIC2_GICD_IPRIORITYR12_INT1_SHIFT 0xb
#define ICP_ICP_QGIC2_GICD_IPRIORITYR12_UNUSED2_MASK 0x70000
#define ICP_ICP_QGIC2_GICD_IPRIORITYR12_UNUSED2_SHIFT 0x10
#define ICP_ICP_QGIC2_GICD_IPRIORITYR12_INT2_MASK 0xf80000
#define ICP_ICP_QGIC2_GICD_IPRIORITYR12_INT2_SHIFT 0x13
#define ICP_ICP_QGIC2_GICD_IPRIORITYR12_UNUSED3_MASK 0x7000000
#define ICP_ICP_QGIC2_GICD_IPRIORITYR12_UNUSED3_SHIFT 0x18
#define ICP_ICP_QGIC2_GICD_IPRIORITYR12_INT3_MASK 0xf8000000
#define ICP_ICP_QGIC2_GICD_IPRIORITYR12_INT3_SHIFT 0x1b

#define regICP_ICP_QGIC2_GICD_IPRIORITYR13 0x434  /*register offset*/
#define ICP_ICP_QGIC2_GICD_IPRIORITYR13_UNUSED0_MASK 0x7
#define ICP_ICP_QGIC2_GICD_IPRIORITYR13_UNUSED0_SHIFT 0x0
#define ICP_ICP_QGIC2_GICD_IPRIORITYR13_INT0_MASK 0xf8
#define ICP_ICP_QGIC2_GICD_IPRIORITYR13_INT0_SHIFT 0x3
#define ICP_ICP_QGIC2_GICD_IPRIORITYR13_UNUSED1_MASK 0x700
#define ICP_ICP_QGIC2_GICD_IPRIORITYR13_UNUSED1_SHIFT 0x8
#define ICP_ICP_QGIC2_GICD_IPRIORITYR13_INT1_MASK 0xf800
#define ICP_ICP_QGIC2_GICD_IPRIORITYR13_INT1_SHIFT 0xb
#define ICP_ICP_QGIC2_GICD_IPRIORITYR13_UNUSED2_MASK 0x70000
#define ICP_ICP_QGIC2_GICD_IPRIORITYR13_UNUSED2_SHIFT 0x10
#define ICP_ICP_QGIC2_GICD_IPRIORITYR13_INT2_MASK 0xf80000
#define ICP_ICP_QGIC2_GICD_IPRIORITYR13_INT2_SHIFT 0x13
#define ICP_ICP_QGIC2_GICD_IPRIORITYR13_UNUSED3_MASK 0x7000000
#define ICP_ICP_QGIC2_GICD_IPRIORITYR13_UNUSED3_SHIFT 0x18
#define ICP_ICP_QGIC2_GICD_IPRIORITYR13_INT3_MASK 0xf8000000
#define ICP_ICP_QGIC2_GICD_IPRIORITYR13_INT3_SHIFT 0x1b

#define regICP_ICP_QGIC2_GICD_IPRIORITYR14 0x438  /*register offset*/
#define ICP_ICP_QGIC2_GICD_IPRIORITYR14_UNUSED0_MASK 0x7
#define ICP_ICP_QGIC2_GICD_IPRIORITYR14_UNUSED0_SHIFT 0x0
#define ICP_ICP_QGIC2_GICD_IPRIORITYR14_INT0_MASK 0xf8
#define ICP_ICP_QGIC2_GICD_IPRIORITYR14_INT0_SHIFT 0x3
#define ICP_ICP_QGIC2_GICD_IPRIORITYR14_UNUSED1_MASK 0x700
#define ICP_ICP_QGIC2_GICD_IPRIORITYR14_UNUSED1_SHIFT 0x8
#define ICP_ICP_QGIC2_GICD_IPRIORITYR14_INT1_MASK 0xf800
#define ICP_ICP_QGIC2_GICD_IPRIORITYR14_INT1_SHIFT 0xb
#define ICP_ICP_QGIC2_GICD_IPRIORITYR14_UNUSED2_MASK 0x70000
#define ICP_ICP_QGIC2_GICD_IPRIORITYR14_UNUSED2_SHIFT 0x10
#define ICP_ICP_QGIC2_GICD_IPRIORITYR14_INT2_MASK 0xf80000
#define ICP_ICP_QGIC2_GICD_IPRIORITYR14_INT2_SHIFT 0x13
#define ICP_ICP_QGIC2_GICD_IPRIORITYR14_UNUSED3_MASK 0x7000000
#define ICP_ICP_QGIC2_GICD_IPRIORITYR14_UNUSED3_SHIFT 0x18
#define ICP_ICP_QGIC2_GICD_IPRIORITYR14_INT3_MASK 0xf8000000
#define ICP_ICP_QGIC2_GICD_IPRIORITYR14_INT3_SHIFT 0x1b

#define regICP_ICP_QGIC2_GICD_IPRIORITYR15 0x43c  /*register offset*/
#define ICP_ICP_QGIC2_GICD_IPRIORITYR15_UNUSED0_MASK 0x7
#define ICP_ICP_QGIC2_GICD_IPRIORITYR15_UNUSED0_SHIFT 0x0
#define ICP_ICP_QGIC2_GICD_IPRIORITYR15_INT0_MASK 0xf8
#define ICP_ICP_QGIC2_GICD_IPRIORITYR15_INT0_SHIFT 0x3
#define ICP_ICP_QGIC2_GICD_IPRIORITYR15_UNUSED1_MASK 0x700
#define ICP_ICP_QGIC2_GICD_IPRIORITYR15_UNUSED1_SHIFT 0x8
#define ICP_ICP_QGIC2_GICD_IPRIORITYR15_INT1_MASK 0xf800
#define ICP_ICP_QGIC2_GICD_IPRIORITYR15_INT1_SHIFT 0xb
#define ICP_ICP_QGIC2_GICD_IPRIORITYR15_UNUSED2_MASK 0x70000
#define ICP_ICP_QGIC2_GICD_IPRIORITYR15_UNUSED2_SHIFT 0x10
#define ICP_ICP_QGIC2_GICD_IPRIORITYR15_INT2_MASK 0xf80000
#define ICP_ICP_QGIC2_GICD_IPRIORITYR15_INT2_SHIFT 0x13
#define ICP_ICP_QGIC2_GICD_IPRIORITYR15_UNUSED3_MASK 0x7000000
#define ICP_ICP_QGIC2_GICD_IPRIORITYR15_UNUSED3_SHIFT 0x18
#define ICP_ICP_QGIC2_GICD_IPRIORITYR15_INT3_MASK 0xf8000000
#define ICP_ICP_QGIC2_GICD_IPRIORITYR15_INT3_SHIFT 0x1b

#define regICP_ICP_QGIC2_GICD_IPRIORITYR16 0x440  /*register offset*/
#define ICP_ICP_QGIC2_GICD_IPRIORITYR16_UNUSED0_MASK 0x7
#define ICP_ICP_QGIC2_GICD_IPRIORITYR16_UNUSED0_SHIFT 0x0
#define ICP_ICP_QGIC2_GICD_IPRIORITYR16_INT0_MASK 0xf8
#define ICP_ICP_QGIC2_GICD_IPRIORITYR16_INT0_SHIFT 0x3
#define ICP_ICP_QGIC2_GICD_IPRIORITYR16_UNUSED1_MASK 0x700
#define ICP_ICP_QGIC2_GICD_IPRIORITYR16_UNUSED1_SHIFT 0x8
#define ICP_ICP_QGIC2_GICD_IPRIORITYR16_INT1_MASK 0xf800
#define ICP_ICP_QGIC2_GICD_IPRIORITYR16_INT1_SHIFT 0xb
#define ICP_ICP_QGIC2_GICD_IPRIORITYR16_UNUSED2_MASK 0x70000
#define ICP_ICP_QGIC2_GICD_IPRIORITYR16_UNUSED2_SHIFT 0x10
#define ICP_ICP_QGIC2_GICD_IPRIORITYR16_INT2_MASK 0xf80000
#define ICP_ICP_QGIC2_GICD_IPRIORITYR16_INT2_SHIFT 0x13
#define ICP_ICP_QGIC2_GICD_IPRIORITYR16_UNUSED3_MASK 0x7000000
#define ICP_ICP_QGIC2_GICD_IPRIORITYR16_UNUSED3_SHIFT 0x18
#define ICP_ICP_QGIC2_GICD_IPRIORITYR16_INT3_MASK 0xf8000000
#define ICP_ICP_QGIC2_GICD_IPRIORITYR16_INT3_SHIFT 0x1b

#define regICP_ICP_QGIC2_GICD_IPRIORITYR17 0x444  /*register offset*/
#define ICP_ICP_QGIC2_GICD_IPRIORITYR17_UNUSED0_MASK 0x7
#define ICP_ICP_QGIC2_GICD_IPRIORITYR17_UNUSED0_SHIFT 0x0
#define ICP_ICP_QGIC2_GICD_IPRIORITYR17_INT0_MASK 0xf8
#define ICP_ICP_QGIC2_GICD_IPRIORITYR17_INT0_SHIFT 0x3
#define ICP_ICP_QGIC2_GICD_IPRIORITYR17_UNUSED1_MASK 0x700
#define ICP_ICP_QGIC2_GICD_IPRIORITYR17_UNUSED1_SHIFT 0x8
#define ICP_ICP_QGIC2_GICD_IPRIORITYR17_INT1_MASK 0xf800
#define ICP_ICP_QGIC2_GICD_IPRIORITYR17_INT1_SHIFT 0xb
#define ICP_ICP_QGIC2_GICD_IPRIORITYR17_UNUSED2_MASK 0x70000
#define ICP_ICP_QGIC2_GICD_IPRIORITYR17_UNUSED2_SHIFT 0x10
#define ICP_ICP_QGIC2_GICD_IPRIORITYR17_INT2_MASK 0xf80000
#define ICP_ICP_QGIC2_GICD_IPRIORITYR17_INT2_SHIFT 0x13
#define ICP_ICP_QGIC2_GICD_IPRIORITYR17_UNUSED3_MASK 0x7000000
#define ICP_ICP_QGIC2_GICD_IPRIORITYR17_UNUSED3_SHIFT 0x18
#define ICP_ICP_QGIC2_GICD_IPRIORITYR17_INT3_MASK 0xf8000000
#define ICP_ICP_QGIC2_GICD_IPRIORITYR17_INT3_SHIFT 0x1b

#define regICP_ICP_QGIC2_GICD_IPRIORITYR18 0x448  /*register offset*/
#define ICP_ICP_QGIC2_GICD_IPRIORITYR18_UNUSED0_MASK 0x7
#define ICP_ICP_QGIC2_GICD_IPRIORITYR18_UNUSED0_SHIFT 0x0
#define ICP_ICP_QGIC2_GICD_IPRIORITYR18_INT0_MASK 0xf8
#define ICP_ICP_QGIC2_GICD_IPRIORITYR18_INT0_SHIFT 0x3
#define ICP_ICP_QGIC2_GICD_IPRIORITYR18_UNUSED1_MASK 0x700
#define ICP_ICP_QGIC2_GICD_IPRIORITYR18_UNUSED1_SHIFT 0x8
#define ICP_ICP_QGIC2_GICD_IPRIORITYR18_INT1_MASK 0xf800
#define ICP_ICP_QGIC2_GICD_IPRIORITYR18_INT1_SHIFT 0xb
#define ICP_ICP_QGIC2_GICD_IPRIORITYR18_UNUSED2_MASK 0x70000
#define ICP_ICP_QGIC2_GICD_IPRIORITYR18_UNUSED2_SHIFT 0x10
#define ICP_ICP_QGIC2_GICD_IPRIORITYR18_INT2_MASK 0xf80000
#define ICP_ICP_QGIC2_GICD_IPRIORITYR18_INT2_SHIFT 0x13
#define ICP_ICP_QGIC2_GICD_IPRIORITYR18_UNUSED3_MASK 0x7000000
#define ICP_ICP_QGIC2_GICD_IPRIORITYR18_UNUSED3_SHIFT 0x18
#define ICP_ICP_QGIC2_GICD_IPRIORITYR18_INT3_MASK 0xf8000000
#define ICP_ICP_QGIC2_GICD_IPRIORITYR18_INT3_SHIFT 0x1b

#define regICP_ICP_QGIC2_GICD_IPRIORITYR19 0x44c  /*register offset*/
#define ICP_ICP_QGIC2_GICD_IPRIORITYR19_UNUSED0_MASK 0x7
#define ICP_ICP_QGIC2_GICD_IPRIORITYR19_UNUSED0_SHIFT 0x0
#define ICP_ICP_QGIC2_GICD_IPRIORITYR19_INT0_MASK 0xf8
#define ICP_ICP_QGIC2_GICD_IPRIORITYR19_INT0_SHIFT 0x3
#define ICP_ICP_QGIC2_GICD_IPRIORITYR19_UNUSED1_MASK 0x700
#define ICP_ICP_QGIC2_GICD_IPRIORITYR19_UNUSED1_SHIFT 0x8
#define ICP_ICP_QGIC2_GICD_IPRIORITYR19_INT1_MASK 0xf800
#define ICP_ICP_QGIC2_GICD_IPRIORITYR19_INT1_SHIFT 0xb
#define ICP_ICP_QGIC2_GICD_IPRIORITYR19_UNUSED2_MASK 0x70000
#define ICP_ICP_QGIC2_GICD_IPRIORITYR19_UNUSED2_SHIFT 0x10
#define ICP_ICP_QGIC2_GICD_IPRIORITYR19_INT2_MASK 0xf80000
#define ICP_ICP_QGIC2_GICD_IPRIORITYR19_INT2_SHIFT 0x13
#define ICP_ICP_QGIC2_GICD_IPRIORITYR19_UNUSED3_MASK 0x7000000
#define ICP_ICP_QGIC2_GICD_IPRIORITYR19_UNUSED3_SHIFT 0x18
#define ICP_ICP_QGIC2_GICD_IPRIORITYR19_INT3_MASK 0xf8000000
#define ICP_ICP_QGIC2_GICD_IPRIORITYR19_INT3_SHIFT 0x1b

#define regICP_ICP_QGIC2_GICD_IPRIORITYR20 0x450  /*register offset*/
#define ICP_ICP_QGIC2_GICD_IPRIORITYR20_UNUSED0_MASK 0x7
#define ICP_ICP_QGIC2_GICD_IPRIORITYR20_UNUSED0_SHIFT 0x0
#define ICP_ICP_QGIC2_GICD_IPRIORITYR20_INT0_MASK 0xf8
#define ICP_ICP_QGIC2_GICD_IPRIORITYR20_INT0_SHIFT 0x3
#define ICP_ICP_QGIC2_GICD_IPRIORITYR20_UNUSED1_MASK 0x700
#define ICP_ICP_QGIC2_GICD_IPRIORITYR20_UNUSED1_SHIFT 0x8
#define ICP_ICP_QGIC2_GICD_IPRIORITYR20_INT1_MASK 0xf800
#define ICP_ICP_QGIC2_GICD_IPRIORITYR20_INT1_SHIFT 0xb
#define ICP_ICP_QGIC2_GICD_IPRIORITYR20_UNUSED2_MASK 0x70000
#define ICP_ICP_QGIC2_GICD_IPRIORITYR20_UNUSED2_SHIFT 0x10
#define ICP_ICP_QGIC2_GICD_IPRIORITYR20_INT2_MASK 0xf80000
#define ICP_ICP_QGIC2_GICD_IPRIORITYR20_INT2_SHIFT 0x13
#define ICP_ICP_QGIC2_GICD_IPRIORITYR20_UNUSED3_MASK 0x7000000
#define ICP_ICP_QGIC2_GICD_IPRIORITYR20_UNUSED3_SHIFT 0x18
#define ICP_ICP_QGIC2_GICD_IPRIORITYR20_INT3_MASK 0xf8000000
#define ICP_ICP_QGIC2_GICD_IPRIORITYR20_INT3_SHIFT 0x1b

#define regICP_ICP_QGIC2_GICD_IPRIORITYR21 0x454  /*register offset*/
#define ICP_ICP_QGIC2_GICD_IPRIORITYR21_UNUSED0_MASK 0x7
#define ICP_ICP_QGIC2_GICD_IPRIORITYR21_UNUSED0_SHIFT 0x0
#define ICP_ICP_QGIC2_GICD_IPRIORITYR21_INT0_MASK 0xf8
#define ICP_ICP_QGIC2_GICD_IPRIORITYR21_INT0_SHIFT 0x3
#define ICP_ICP_QGIC2_GICD_IPRIORITYR21_UNUSED1_MASK 0x700
#define ICP_ICP_QGIC2_GICD_IPRIORITYR21_UNUSED1_SHIFT 0x8
#define ICP_ICP_QGIC2_GICD_IPRIORITYR21_INT1_MASK 0xf800
#define ICP_ICP_QGIC2_GICD_IPRIORITYR21_INT1_SHIFT 0xb
#define ICP_ICP_QGIC2_GICD_IPRIORITYR21_UNUSED2_MASK 0x70000
#define ICP_ICP_QGIC2_GICD_IPRIORITYR21_UNUSED2_SHIFT 0x10
#define ICP_ICP_QGIC2_GICD_IPRIORITYR21_INT2_MASK 0xf80000
#define ICP_ICP_QGIC2_GICD_IPRIORITYR21_INT2_SHIFT 0x13
#define ICP_ICP_QGIC2_GICD_IPRIORITYR21_UNUSED3_MASK 0x7000000
#define ICP_ICP_QGIC2_GICD_IPRIORITYR21_UNUSED3_SHIFT 0x18
#define ICP_ICP_QGIC2_GICD_IPRIORITYR21_INT3_MASK 0xf8000000
#define ICP_ICP_QGIC2_GICD_IPRIORITYR21_INT3_SHIFT 0x1b

#define regICP_ICP_QGIC2_GICD_IPRIORITYR22 0x458  /*register offset*/
#define ICP_ICP_QGIC2_GICD_IPRIORITYR22_UNUSED0_MASK 0x7
#define ICP_ICP_QGIC2_GICD_IPRIORITYR22_UNUSED0_SHIFT 0x0
#define ICP_ICP_QGIC2_GICD_IPRIORITYR22_INT0_MASK 0xf8
#define ICP_ICP_QGIC2_GICD_IPRIORITYR22_INT0_SHIFT 0x3
#define ICP_ICP_QGIC2_GICD_IPRIORITYR22_UNUSED1_MASK 0x700
#define ICP_ICP_QGIC2_GICD_IPRIORITYR22_UNUSED1_SHIFT 0x8
#define ICP_ICP_QGIC2_GICD_IPRIORITYR22_INT1_MASK 0xf800
#define ICP_ICP_QGIC2_GICD_IPRIORITYR22_INT1_SHIFT 0xb
#define ICP_ICP_QGIC2_GICD_IPRIORITYR22_UNUSED2_MASK 0x70000
#define ICP_ICP_QGIC2_GICD_IPRIORITYR22_UNUSED2_SHIFT 0x10
#define ICP_ICP_QGIC2_GICD_IPRIORITYR22_INT2_MASK 0xf80000
#define ICP_ICP_QGIC2_GICD_IPRIORITYR22_INT2_SHIFT 0x13
#define ICP_ICP_QGIC2_GICD_IPRIORITYR22_UNUSED3_MASK 0x7000000
#define ICP_ICP_QGIC2_GICD_IPRIORITYR22_UNUSED3_SHIFT 0x18
#define ICP_ICP_QGIC2_GICD_IPRIORITYR22_INT3_MASK 0xf8000000
#define ICP_ICP_QGIC2_GICD_IPRIORITYR22_INT3_SHIFT 0x1b

#define regICP_ICP_QGIC2_GICD_IPRIORITYR23 0x45c  /*register offset*/
#define ICP_ICP_QGIC2_GICD_IPRIORITYR23_UNUSED0_MASK 0x7
#define ICP_ICP_QGIC2_GICD_IPRIORITYR23_UNUSED0_SHIFT 0x0
#define ICP_ICP_QGIC2_GICD_IPRIORITYR23_INT0_MASK 0xf8
#define ICP_ICP_QGIC2_GICD_IPRIORITYR23_INT0_SHIFT 0x3
#define ICP_ICP_QGIC2_GICD_IPRIORITYR23_UNUSED1_MASK 0x700
#define ICP_ICP_QGIC2_GICD_IPRIORITYR23_UNUSED1_SHIFT 0x8
#define ICP_ICP_QGIC2_GICD_IPRIORITYR23_INT1_MASK 0xf800
#define ICP_ICP_QGIC2_GICD_IPRIORITYR23_INT1_SHIFT 0xb
#define ICP_ICP_QGIC2_GICD_IPRIORITYR23_UNUSED2_MASK 0x70000
#define ICP_ICP_QGIC2_GICD_IPRIORITYR23_UNUSED2_SHIFT 0x10
#define ICP_ICP_QGIC2_GICD_IPRIORITYR23_INT2_MASK 0xf80000
#define ICP_ICP_QGIC2_GICD_IPRIORITYR23_INT2_SHIFT 0x13
#define ICP_ICP_QGIC2_GICD_IPRIORITYR23_UNUSED3_MASK 0x7000000
#define ICP_ICP_QGIC2_GICD_IPRIORITYR23_UNUSED3_SHIFT 0x18
#define ICP_ICP_QGIC2_GICD_IPRIORITYR23_INT3_MASK 0xf8000000
#define ICP_ICP_QGIC2_GICD_IPRIORITYR23_INT3_SHIFT 0x1b

#define regICP_ICP_QGIC2_GICD_ITARGETSR0 0x800  /*register offset*/
#define ICP_ICP_QGIC2_GICD_ITARGETSR0_INT0_MASK 0xff
#define ICP_ICP_QGIC2_GICD_ITARGETSR0_INT0_SHIFT 0x0
#define ICP_ICP_QGIC2_GICD_ITARGETSR0_INT1_MASK 0xff00
#define ICP_ICP_QGIC2_GICD_ITARGETSR0_INT1_SHIFT 0x8
#define ICP_ICP_QGIC2_GICD_ITARGETSR0_INT2_MASK 0xff0000
#define ICP_ICP_QGIC2_GICD_ITARGETSR0_INT2_SHIFT 0x10
#define ICP_ICP_QGIC2_GICD_ITARGETSR0_INT3_MASK 0xff000000
#define ICP_ICP_QGIC2_GICD_ITARGETSR0_INT3_SHIFT 0x18

#define regICP_ICP_QGIC2_GICD_ITARGETSR1 0x804  /*register offset*/
#define ICP_ICP_QGIC2_GICD_ITARGETSR1_INT0_MASK 0xff
#define ICP_ICP_QGIC2_GICD_ITARGETSR1_INT0_SHIFT 0x0
#define ICP_ICP_QGIC2_GICD_ITARGETSR1_INT1_MASK 0xff00
#define ICP_ICP_QGIC2_GICD_ITARGETSR1_INT1_SHIFT 0x8
#define ICP_ICP_QGIC2_GICD_ITARGETSR1_INT2_MASK 0xff0000
#define ICP_ICP_QGIC2_GICD_ITARGETSR1_INT2_SHIFT 0x10
#define ICP_ICP_QGIC2_GICD_ITARGETSR1_INT3_MASK 0xff000000
#define ICP_ICP_QGIC2_GICD_ITARGETSR1_INT3_SHIFT 0x18

#define regICP_ICP_QGIC2_GICD_ITARGETSR2 0x808  /*register offset*/
#define ICP_ICP_QGIC2_GICD_ITARGETSR2_INT0_MASK 0xff
#define ICP_ICP_QGIC2_GICD_ITARGETSR2_INT0_SHIFT 0x0
#define ICP_ICP_QGIC2_GICD_ITARGETSR2_INT1_MASK 0xff00
#define ICP_ICP_QGIC2_GICD_ITARGETSR2_INT1_SHIFT 0x8
#define ICP_ICP_QGIC2_GICD_ITARGETSR2_INT2_MASK 0xff0000
#define ICP_ICP_QGIC2_GICD_ITARGETSR2_INT2_SHIFT 0x10
#define ICP_ICP_QGIC2_GICD_ITARGETSR2_INT3_MASK 0xff000000
#define ICP_ICP_QGIC2_GICD_ITARGETSR2_INT3_SHIFT 0x18

#define regICP_ICP_QGIC2_GICD_ITARGETSR3 0x80c  /*register offset*/
#define ICP_ICP_QGIC2_GICD_ITARGETSR3_INT0_MASK 0xff
#define ICP_ICP_QGIC2_GICD_ITARGETSR3_INT0_SHIFT 0x0
#define ICP_ICP_QGIC2_GICD_ITARGETSR3_INT1_MASK 0xff00
#define ICP_ICP_QGIC2_GICD_ITARGETSR3_INT1_SHIFT 0x8
#define ICP_ICP_QGIC2_GICD_ITARGETSR3_INT2_MASK 0xff0000
#define ICP_ICP_QGIC2_GICD_ITARGETSR3_INT2_SHIFT 0x10
#define ICP_ICP_QGIC2_GICD_ITARGETSR3_INT3_MASK 0xff000000
#define ICP_ICP_QGIC2_GICD_ITARGETSR3_INT3_SHIFT 0x18

#define regICP_ICP_QGIC2_GICD_ITARGETSR4 0x810  /*register offset*/
#define ICP_ICP_QGIC2_GICD_ITARGETSR4_INT0_MASK 0xff
#define ICP_ICP_QGIC2_GICD_ITARGETSR4_INT0_SHIFT 0x0
#define ICP_ICP_QGIC2_GICD_ITARGETSR4_INT1_MASK 0xff00
#define ICP_ICP_QGIC2_GICD_ITARGETSR4_INT1_SHIFT 0x8
#define ICP_ICP_QGIC2_GICD_ITARGETSR4_INT2_MASK 0xff0000
#define ICP_ICP_QGIC2_GICD_ITARGETSR4_INT2_SHIFT 0x10
#define ICP_ICP_QGIC2_GICD_ITARGETSR4_INT3_MASK 0xff000000
#define ICP_ICP_QGIC2_GICD_ITARGETSR4_INT3_SHIFT 0x18

#define regICP_ICP_QGIC2_GICD_ITARGETSR5 0x814  /*register offset*/
#define ICP_ICP_QGIC2_GICD_ITARGETSR5_INT0_MASK 0xff
#define ICP_ICP_QGIC2_GICD_ITARGETSR5_INT0_SHIFT 0x0
#define ICP_ICP_QGIC2_GICD_ITARGETSR5_INT1_MASK 0xff00
#define ICP_ICP_QGIC2_GICD_ITARGETSR5_INT1_SHIFT 0x8
#define ICP_ICP_QGIC2_GICD_ITARGETSR5_INT2_MASK 0xff0000
#define ICP_ICP_QGIC2_GICD_ITARGETSR5_INT2_SHIFT 0x10
#define ICP_ICP_QGIC2_GICD_ITARGETSR5_INT3_MASK 0xff000000
#define ICP_ICP_QGIC2_GICD_ITARGETSR5_INT3_SHIFT 0x18

#define regICP_ICP_QGIC2_GICD_ITARGETSR6 0x818  /*register offset*/
#define ICP_ICP_QGIC2_GICD_ITARGETSR6_INT0_MASK 0xff
#define ICP_ICP_QGIC2_GICD_ITARGETSR6_INT0_SHIFT 0x0
#define ICP_ICP_QGIC2_GICD_ITARGETSR6_INT1_MASK 0xff00
#define ICP_ICP_QGIC2_GICD_ITARGETSR6_INT1_SHIFT 0x8
#define ICP_ICP_QGIC2_GICD_ITARGETSR6_INT2_MASK 0xff0000
#define ICP_ICP_QGIC2_GICD_ITARGETSR6_INT2_SHIFT 0x10
#define ICP_ICP_QGIC2_GICD_ITARGETSR6_INT3_MASK 0xff000000
#define ICP_ICP_QGIC2_GICD_ITARGETSR6_INT3_SHIFT 0x18

#define regICP_ICP_QGIC2_GICD_ITARGETSR7 0x81c  /*register offset*/
#define ICP_ICP_QGIC2_GICD_ITARGETSR7_INT0_MASK 0xff
#define ICP_ICP_QGIC2_GICD_ITARGETSR7_INT0_SHIFT 0x0
#define ICP_ICP_QGIC2_GICD_ITARGETSR7_INT1_MASK 0xff00
#define ICP_ICP_QGIC2_GICD_ITARGETSR7_INT1_SHIFT 0x8
#define ICP_ICP_QGIC2_GICD_ITARGETSR7_INT2_MASK 0xff0000
#define ICP_ICP_QGIC2_GICD_ITARGETSR7_INT2_SHIFT 0x10
#define ICP_ICP_QGIC2_GICD_ITARGETSR7_INT3_MASK 0xff000000
#define ICP_ICP_QGIC2_GICD_ITARGETSR7_INT3_SHIFT 0x18

#define regICP_ICP_QGIC2_GICD_ITARGETSR8 0x820  /*register offset*/
#define ICP_ICP_QGIC2_GICD_ITARGETSR8_INT0_MASK 0xff
#define ICP_ICP_QGIC2_GICD_ITARGETSR8_INT0_SHIFT 0x0
#define ICP_ICP_QGIC2_GICD_ITARGETSR8_INT1_MASK 0xff00
#define ICP_ICP_QGIC2_GICD_ITARGETSR8_INT1_SHIFT 0x8
#define ICP_ICP_QGIC2_GICD_ITARGETSR8_INT2_MASK 0xff0000
#define ICP_ICP_QGIC2_GICD_ITARGETSR8_INT2_SHIFT 0x10
#define ICP_ICP_QGIC2_GICD_ITARGETSR8_INT3_MASK 0xff000000
#define ICP_ICP_QGIC2_GICD_ITARGETSR8_INT3_SHIFT 0x18

#define regICP_ICP_QGIC2_GICD_ITARGETSR9 0x824  /*register offset*/
#define ICP_ICP_QGIC2_GICD_ITARGETSR9_INT0_MASK 0xff
#define ICP_ICP_QGIC2_GICD_ITARGETSR9_INT0_SHIFT 0x0
#define ICP_ICP_QGIC2_GICD_ITARGETSR9_INT1_MASK 0xff00
#define ICP_ICP_QGIC2_GICD_ITARGETSR9_INT1_SHIFT 0x8
#define ICP_ICP_QGIC2_GICD_ITARGETSR9_INT2_MASK 0xff0000
#define ICP_ICP_QGIC2_GICD_ITARGETSR9_INT2_SHIFT 0x10
#define ICP_ICP_QGIC2_GICD_ITARGETSR9_INT3_MASK 0xff000000
#define ICP_ICP_QGIC2_GICD_ITARGETSR9_INT3_SHIFT 0x18

#define regICP_ICP_QGIC2_GICD_ITARGETSR10 0x828  /*register offset*/
#define ICP_ICP_QGIC2_GICD_ITARGETSR10_INT0_MASK 0xff
#define ICP_ICP_QGIC2_GICD_ITARGETSR10_INT0_SHIFT 0x0
#define ICP_ICP_QGIC2_GICD_ITARGETSR10_INT1_MASK 0xff00
#define ICP_ICP_QGIC2_GICD_ITARGETSR10_INT1_SHIFT 0x8
#define ICP_ICP_QGIC2_GICD_ITARGETSR10_INT2_MASK 0xff0000
#define ICP_ICP_QGIC2_GICD_ITARGETSR10_INT2_SHIFT 0x10
#define ICP_ICP_QGIC2_GICD_ITARGETSR10_INT3_MASK 0xff000000
#define ICP_ICP_QGIC2_GICD_ITARGETSR10_INT3_SHIFT 0x18

#define regICP_ICP_QGIC2_GICD_ITARGETSR11 0x82c  /*register offset*/
#define ICP_ICP_QGIC2_GICD_ITARGETSR11_INT0_MASK 0xff
#define ICP_ICP_QGIC2_GICD_ITARGETSR11_INT0_SHIFT 0x0
#define ICP_ICP_QGIC2_GICD_ITARGETSR11_INT1_MASK 0xff00
#define ICP_ICP_QGIC2_GICD_ITARGETSR11_INT1_SHIFT 0x8
#define ICP_ICP_QGIC2_GICD_ITARGETSR11_INT2_MASK 0xff0000
#define ICP_ICP_QGIC2_GICD_ITARGETSR11_INT2_SHIFT 0x10
#define ICP_ICP_QGIC2_GICD_ITARGETSR11_INT3_MASK 0xff000000
#define ICP_ICP_QGIC2_GICD_ITARGETSR11_INT3_SHIFT 0x18

#define regICP_ICP_QGIC2_GICD_ITARGETSR12 0x830  /*register offset*/
#define ICP_ICP_QGIC2_GICD_ITARGETSR12_INT0_MASK 0xff
#define ICP_ICP_QGIC2_GICD_ITARGETSR12_INT0_SHIFT 0x0
#define ICP_ICP_QGIC2_GICD_ITARGETSR12_INT1_MASK 0xff00
#define ICP_ICP_QGIC2_GICD_ITARGETSR12_INT1_SHIFT 0x8
#define ICP_ICP_QGIC2_GICD_ITARGETSR12_INT2_MASK 0xff0000
#define ICP_ICP_QGIC2_GICD_ITARGETSR12_INT2_SHIFT 0x10
#define ICP_ICP_QGIC2_GICD_ITARGETSR12_INT3_MASK 0xff000000
#define ICP_ICP_QGIC2_GICD_ITARGETSR12_INT3_SHIFT 0x18

#define regICP_ICP_QGIC2_GICD_ITARGETSR13 0x834  /*register offset*/
#define ICP_ICP_QGIC2_GICD_ITARGETSR13_INT0_MASK 0xff
#define ICP_ICP_QGIC2_GICD_ITARGETSR13_INT0_SHIFT 0x0
#define ICP_ICP_QGIC2_GICD_ITARGETSR13_INT1_MASK 0xff00
#define ICP_ICP_QGIC2_GICD_ITARGETSR13_INT1_SHIFT 0x8
#define ICP_ICP_QGIC2_GICD_ITARGETSR13_INT2_MASK 0xff0000
#define ICP_ICP_QGIC2_GICD_ITARGETSR13_INT2_SHIFT 0x10
#define ICP_ICP_QGIC2_GICD_ITARGETSR13_INT3_MASK 0xff000000
#define ICP_ICP_QGIC2_GICD_ITARGETSR13_INT3_SHIFT 0x18

#define regICP_ICP_QGIC2_GICD_ITARGETSR14 0x838  /*register offset*/
#define ICP_ICP_QGIC2_GICD_ITARGETSR14_INT0_MASK 0xff
#define ICP_ICP_QGIC2_GICD_ITARGETSR14_INT0_SHIFT 0x0
#define ICP_ICP_QGIC2_GICD_ITARGETSR14_INT1_MASK 0xff00
#define ICP_ICP_QGIC2_GICD_ITARGETSR14_INT1_SHIFT 0x8
#define ICP_ICP_QGIC2_GICD_ITARGETSR14_INT2_MASK 0xff0000
#define ICP_ICP_QGIC2_GICD_ITARGETSR14_INT2_SHIFT 0x10
#define ICP_ICP_QGIC2_GICD_ITARGETSR14_INT3_MASK 0xff000000
#define ICP_ICP_QGIC2_GICD_ITARGETSR14_INT3_SHIFT 0x18

#define regICP_ICP_QGIC2_GICD_ITARGETSR15 0x83c  /*register offset*/
#define ICP_ICP_QGIC2_GICD_ITARGETSR15_INT0_MASK 0xff
#define ICP_ICP_QGIC2_GICD_ITARGETSR15_INT0_SHIFT 0x0
#define ICP_ICP_QGIC2_GICD_ITARGETSR15_INT1_MASK 0xff00
#define ICP_ICP_QGIC2_GICD_ITARGETSR15_INT1_SHIFT 0x8
#define ICP_ICP_QGIC2_GICD_ITARGETSR15_INT2_MASK 0xff0000
#define ICP_ICP_QGIC2_GICD_ITARGETSR15_INT2_SHIFT 0x10
#define ICP_ICP_QGIC2_GICD_ITARGETSR15_INT3_MASK 0xff000000
#define ICP_ICP_QGIC2_GICD_ITARGETSR15_INT3_SHIFT 0x18

#define regICP_ICP_QGIC2_GICD_ITARGETSR16 0x840  /*register offset*/
#define ICP_ICP_QGIC2_GICD_ITARGETSR16_INT0_MASK 0xff
#define ICP_ICP_QGIC2_GICD_ITARGETSR16_INT0_SHIFT 0x0
#define ICP_ICP_QGIC2_GICD_ITARGETSR16_INT1_MASK 0xff00
#define ICP_ICP_QGIC2_GICD_ITARGETSR16_INT1_SHIFT 0x8
#define ICP_ICP_QGIC2_GICD_ITARGETSR16_INT2_MASK 0xff0000
#define ICP_ICP_QGIC2_GICD_ITARGETSR16_INT2_SHIFT 0x10
#define ICP_ICP_QGIC2_GICD_ITARGETSR16_INT3_MASK 0xff000000
#define ICP_ICP_QGIC2_GICD_ITARGETSR16_INT3_SHIFT 0x18

#define regICP_ICP_QGIC2_GICD_ITARGETSR17 0x844  /*register offset*/
#define ICP_ICP_QGIC2_GICD_ITARGETSR17_INT0_MASK 0xff
#define ICP_ICP_QGIC2_GICD_ITARGETSR17_INT0_SHIFT 0x0
#define ICP_ICP_QGIC2_GICD_ITARGETSR17_INT1_MASK 0xff00
#define ICP_ICP_QGIC2_GICD_ITARGETSR17_INT1_SHIFT 0x8
#define ICP_ICP_QGIC2_GICD_ITARGETSR17_INT2_MASK 0xff0000
#define ICP_ICP_QGIC2_GICD_ITARGETSR17_INT2_SHIFT 0x10
#define ICP_ICP_QGIC2_GICD_ITARGETSR17_INT3_MASK 0xff000000
#define ICP_ICP_QGIC2_GICD_ITARGETSR17_INT3_SHIFT 0x18

#define regICP_ICP_QGIC2_GICD_ITARGETSR18 0x848  /*register offset*/
#define ICP_ICP_QGIC2_GICD_ITARGETSR18_INT0_MASK 0xff
#define ICP_ICP_QGIC2_GICD_ITARGETSR18_INT0_SHIFT 0x0
#define ICP_ICP_QGIC2_GICD_ITARGETSR18_INT1_MASK 0xff00
#define ICP_ICP_QGIC2_GICD_ITARGETSR18_INT1_SHIFT 0x8
#define ICP_ICP_QGIC2_GICD_ITARGETSR18_INT2_MASK 0xff0000
#define ICP_ICP_QGIC2_GICD_ITARGETSR18_INT2_SHIFT 0x10
#define ICP_ICP_QGIC2_GICD_ITARGETSR18_INT3_MASK 0xff000000
#define ICP_ICP_QGIC2_GICD_ITARGETSR18_INT3_SHIFT 0x18

#define regICP_ICP_QGIC2_GICD_ITARGETSR19 0x84c  /*register offset*/
#define ICP_ICP_QGIC2_GICD_ITARGETSR19_INT0_MASK 0xff
#define ICP_ICP_QGIC2_GICD_ITARGETSR19_INT0_SHIFT 0x0
#define ICP_ICP_QGIC2_GICD_ITARGETSR19_INT1_MASK 0xff00
#define ICP_ICP_QGIC2_GICD_ITARGETSR19_INT1_SHIFT 0x8
#define ICP_ICP_QGIC2_GICD_ITARGETSR19_INT2_MASK 0xff0000
#define ICP_ICP_QGIC2_GICD_ITARGETSR19_INT2_SHIFT 0x10
#define ICP_ICP_QGIC2_GICD_ITARGETSR19_INT3_MASK 0xff000000
#define ICP_ICP_QGIC2_GICD_ITARGETSR19_INT3_SHIFT 0x18

#define regICP_ICP_QGIC2_GICD_ITARGETSR20 0x850  /*register offset*/
#define ICP_ICP_QGIC2_GICD_ITARGETSR20_INT0_MASK 0xff
#define ICP_ICP_QGIC2_GICD_ITARGETSR20_INT0_SHIFT 0x0
#define ICP_ICP_QGIC2_GICD_ITARGETSR20_INT1_MASK 0xff00
#define ICP_ICP_QGIC2_GICD_ITARGETSR20_INT1_SHIFT 0x8
#define ICP_ICP_QGIC2_GICD_ITARGETSR20_INT2_MASK 0xff0000
#define ICP_ICP_QGIC2_GICD_ITARGETSR20_INT2_SHIFT 0x10
#define ICP_ICP_QGIC2_GICD_ITARGETSR20_INT3_MASK 0xff000000
#define ICP_ICP_QGIC2_GICD_ITARGETSR20_INT3_SHIFT 0x18

#define regICP_ICP_QGIC2_GICD_ITARGETSR21 0x854  /*register offset*/
#define ICP_ICP_QGIC2_GICD_ITARGETSR21_INT0_MASK 0xff
#define ICP_ICP_QGIC2_GICD_ITARGETSR21_INT0_SHIFT 0x0
#define ICP_ICP_QGIC2_GICD_ITARGETSR21_INT1_MASK 0xff00
#define ICP_ICP_QGIC2_GICD_ITARGETSR21_INT1_SHIFT 0x8
#define ICP_ICP_QGIC2_GICD_ITARGETSR21_INT2_MASK 0xff0000
#define ICP_ICP_QGIC2_GICD_ITARGETSR21_INT2_SHIFT 0x10
#define ICP_ICP_QGIC2_GICD_ITARGETSR21_INT3_MASK 0xff000000
#define ICP_ICP_QGIC2_GICD_ITARGETSR21_INT3_SHIFT 0x18

#define regICP_ICP_QGIC2_GICD_ITARGETSR22 0x858  /*register offset*/
#define ICP_ICP_QGIC2_GICD_ITARGETSR22_INT0_MASK 0xff
#define ICP_ICP_QGIC2_GICD_ITARGETSR22_INT0_SHIFT 0x0
#define ICP_ICP_QGIC2_GICD_ITARGETSR22_INT1_MASK 0xff00
#define ICP_ICP_QGIC2_GICD_ITARGETSR22_INT1_SHIFT 0x8
#define ICP_ICP_QGIC2_GICD_ITARGETSR22_INT2_MASK 0xff0000
#define ICP_ICP_QGIC2_GICD_ITARGETSR22_INT2_SHIFT 0x10
#define ICP_ICP_QGIC2_GICD_ITARGETSR22_INT3_MASK 0xff000000
#define ICP_ICP_QGIC2_GICD_ITARGETSR22_INT3_SHIFT 0x18

#define regICP_ICP_QGIC2_GICD_ITARGETSR23 0x85c  /*register offset*/
#define ICP_ICP_QGIC2_GICD_ITARGETSR23_INT0_MASK 0xff
#define ICP_ICP_QGIC2_GICD_ITARGETSR23_INT0_SHIFT 0x0
#define ICP_ICP_QGIC2_GICD_ITARGETSR23_INT1_MASK 0xff00
#define ICP_ICP_QGIC2_GICD_ITARGETSR23_INT1_SHIFT 0x8
#define ICP_ICP_QGIC2_GICD_ITARGETSR23_INT2_MASK 0xff0000
#define ICP_ICP_QGIC2_GICD_ITARGETSR23_INT2_SHIFT 0x10
#define ICP_ICP_QGIC2_GICD_ITARGETSR23_INT3_MASK 0xff000000
#define ICP_ICP_QGIC2_GICD_ITARGETSR23_INT3_SHIFT 0x18

#define regICP_ICP_QGIC2_GICD_ICFGR0 0xc00  /*register offset*/
#define ICP_ICP_QGIC2_GICD_ICFGR0_INT0_MASK 0x3
#define ICP_ICP_QGIC2_GICD_ICFGR0_INT0_SHIFT 0x0
#define ICP_ICP_QGIC2_GICD_ICFGR0_INT1_MASK 0xc
#define ICP_ICP_QGIC2_GICD_ICFGR0_INT1_SHIFT 0x2
#define ICP_ICP_QGIC2_GICD_ICFGR0_INT2_MASK 0x30
#define ICP_ICP_QGIC2_GICD_ICFGR0_INT2_SHIFT 0x4
#define ICP_ICP_QGIC2_GICD_ICFGR0_INT3_MASK 0xc0
#define ICP_ICP_QGIC2_GICD_ICFGR0_INT3_SHIFT 0x6
#define ICP_ICP_QGIC2_GICD_ICFGR0_INT4_MASK 0x300
#define ICP_ICP_QGIC2_GICD_ICFGR0_INT4_SHIFT 0x8
#define ICP_ICP_QGIC2_GICD_ICFGR0_INT5_MASK 0xc00
#define ICP_ICP_QGIC2_GICD_ICFGR0_INT5_SHIFT 0xa
#define ICP_ICP_QGIC2_GICD_ICFGR0_INT6_MASK 0x3000
#define ICP_ICP_QGIC2_GICD_ICFGR0_INT6_SHIFT 0xc
#define ICP_ICP_QGIC2_GICD_ICFGR0_INT7_MASK 0xc000
#define ICP_ICP_QGIC2_GICD_ICFGR0_INT7_SHIFT 0xe
#define ICP_ICP_QGIC2_GICD_ICFGR0_INT8_MASK 0x30000
#define ICP_ICP_QGIC2_GICD_ICFGR0_INT8_SHIFT 0x10
#define ICP_ICP_QGIC2_GICD_ICFGR0_INT9_MASK 0xc0000
#define ICP_ICP_QGIC2_GICD_ICFGR0_INT9_SHIFT 0x12
#define ICP_ICP_QGIC2_GICD_ICFGR0_INT10_MASK 0x300000
#define ICP_ICP_QGIC2_GICD_ICFGR0_INT10_SHIFT 0x14
#define ICP_ICP_QGIC2_GICD_ICFGR0_INT11_MASK 0xc00000
#define ICP_ICP_QGIC2_GICD_ICFGR0_INT11_SHIFT 0x16
#define ICP_ICP_QGIC2_GICD_ICFGR0_INT12_MASK 0x3000000
#define ICP_ICP_QGIC2_GICD_ICFGR0_INT12_SHIFT 0x18
#define ICP_ICP_QGIC2_GICD_ICFGR0_INT13_MASK 0xc000000
#define ICP_ICP_QGIC2_GICD_ICFGR0_INT13_SHIFT 0x1a
#define ICP_ICP_QGIC2_GICD_ICFGR0_INT14_MASK 0x30000000
#define ICP_ICP_QGIC2_GICD_ICFGR0_INT14_SHIFT 0x1c
#define ICP_ICP_QGIC2_GICD_ICFGR0_INT15_MASK 0xc0000000
#define ICP_ICP_QGIC2_GICD_ICFGR0_INT15_SHIFT 0x1e

#define regICP_ICP_QGIC2_GICD_ICFGR1 0xc04  /*register offset*/
#define ICP_ICP_QGIC2_GICD_ICFGR1_INT0_MASK 0x3
#define ICP_ICP_QGIC2_GICD_ICFGR1_INT0_SHIFT 0x0
#define ICP_ICP_QGIC2_GICD_ICFGR1_INT1_MASK 0xc
#define ICP_ICP_QGIC2_GICD_ICFGR1_INT1_SHIFT 0x2
#define ICP_ICP_QGIC2_GICD_ICFGR1_INT2_MASK 0x30
#define ICP_ICP_QGIC2_GICD_ICFGR1_INT2_SHIFT 0x4
#define ICP_ICP_QGIC2_GICD_ICFGR1_INT3_MASK 0xc0
#define ICP_ICP_QGIC2_GICD_ICFGR1_INT3_SHIFT 0x6
#define ICP_ICP_QGIC2_GICD_ICFGR1_INT4_MASK 0x300
#define ICP_ICP_QGIC2_GICD_ICFGR1_INT4_SHIFT 0x8
#define ICP_ICP_QGIC2_GICD_ICFGR1_INT5_MASK 0xc00
#define ICP_ICP_QGIC2_GICD_ICFGR1_INT5_SHIFT 0xa
#define ICP_ICP_QGIC2_GICD_ICFGR1_INT6_MASK 0x3000
#define ICP_ICP_QGIC2_GICD_ICFGR1_INT6_SHIFT 0xc
#define ICP_ICP_QGIC2_GICD_ICFGR1_INT7_MASK 0xc000
#define ICP_ICP_QGIC2_GICD_ICFGR1_INT7_SHIFT 0xe
#define ICP_ICP_QGIC2_GICD_ICFGR1_INT8_MASK 0x30000
#define ICP_ICP_QGIC2_GICD_ICFGR1_INT8_SHIFT 0x10
#define ICP_ICP_QGIC2_GICD_ICFGR1_INT9_MASK 0xc0000
#define ICP_ICP_QGIC2_GICD_ICFGR1_INT9_SHIFT 0x12
#define ICP_ICP_QGIC2_GICD_ICFGR1_INT10_MASK 0x300000
#define ICP_ICP_QGIC2_GICD_ICFGR1_INT10_SHIFT 0x14
#define ICP_ICP_QGIC2_GICD_ICFGR1_INT11_MASK 0xc00000
#define ICP_ICP_QGIC2_GICD_ICFGR1_INT11_SHIFT 0x16
#define ICP_ICP_QGIC2_GICD_ICFGR1_INT12_MASK 0x3000000
#define ICP_ICP_QGIC2_GICD_ICFGR1_INT12_SHIFT 0x18
#define ICP_ICP_QGIC2_GICD_ICFGR1_INT13_MASK 0xc000000
#define ICP_ICP_QGIC2_GICD_ICFGR1_INT13_SHIFT 0x1a
#define ICP_ICP_QGIC2_GICD_ICFGR1_INT14_MASK 0x30000000
#define ICP_ICP_QGIC2_GICD_ICFGR1_INT14_SHIFT 0x1c
#define ICP_ICP_QGIC2_GICD_ICFGR1_INT15_MASK 0xc0000000
#define ICP_ICP_QGIC2_GICD_ICFGR1_INT15_SHIFT 0x1e

#define regICP_ICP_QGIC2_GICD_ICFGR2 0xc08  /*register offset*/
#define ICP_ICP_QGIC2_GICD_ICFGR2_INT0_MASK 0x3
#define ICP_ICP_QGIC2_GICD_ICFGR2_INT0_SHIFT 0x0
#define ICP_ICP_QGIC2_GICD_ICFGR2_INT1_MASK 0xc
#define ICP_ICP_QGIC2_GICD_ICFGR2_INT1_SHIFT 0x2
#define ICP_ICP_QGIC2_GICD_ICFGR2_INT2_MASK 0x30
#define ICP_ICP_QGIC2_GICD_ICFGR2_INT2_SHIFT 0x4
#define ICP_ICP_QGIC2_GICD_ICFGR2_INT3_MASK 0xc0
#define ICP_ICP_QGIC2_GICD_ICFGR2_INT3_SHIFT 0x6
#define ICP_ICP_QGIC2_GICD_ICFGR2_INT4_MASK 0x300
#define ICP_ICP_QGIC2_GICD_ICFGR2_INT4_SHIFT 0x8
#define ICP_ICP_QGIC2_GICD_ICFGR2_INT5_MASK 0xc00
#define ICP_ICP_QGIC2_GICD_ICFGR2_INT5_SHIFT 0xa
#define ICP_ICP_QGIC2_GICD_ICFGR2_INT6_MASK 0x3000
#define ICP_ICP_QGIC2_GICD_ICFGR2_INT6_SHIFT 0xc
#define ICP_ICP_QGIC2_GICD_ICFGR2_INT7_MASK 0xc000
#define ICP_ICP_QGIC2_GICD_ICFGR2_INT7_SHIFT 0xe
#define ICP_ICP_QGIC2_GICD_ICFGR2_INT8_MASK 0x30000
#define ICP_ICP_QGIC2_GICD_ICFGR2_INT8_SHIFT 0x10
#define ICP_ICP_QGIC2_GICD_ICFGR2_INT9_MASK 0xc0000
#define ICP_ICP_QGIC2_GICD_ICFGR2_INT9_SHIFT 0x12
#define ICP_ICP_QGIC2_GICD_ICFGR2_INT10_MASK 0x300000
#define ICP_ICP_QGIC2_GICD_ICFGR2_INT10_SHIFT 0x14
#define ICP_ICP_QGIC2_GICD_ICFGR2_INT11_MASK 0xc00000
#define ICP_ICP_QGIC2_GICD_ICFGR2_INT11_SHIFT 0x16
#define ICP_ICP_QGIC2_GICD_ICFGR2_INT12_MASK 0x3000000
#define ICP_ICP_QGIC2_GICD_ICFGR2_INT12_SHIFT 0x18
#define ICP_ICP_QGIC2_GICD_ICFGR2_INT13_MASK 0xc000000
#define ICP_ICP_QGIC2_GICD_ICFGR2_INT13_SHIFT 0x1a
#define ICP_ICP_QGIC2_GICD_ICFGR2_INT14_MASK 0x30000000
#define ICP_ICP_QGIC2_GICD_ICFGR2_INT14_SHIFT 0x1c
#define ICP_ICP_QGIC2_GICD_ICFGR2_INT15_MASK 0xc0000000
#define ICP_ICP_QGIC2_GICD_ICFGR2_INT15_SHIFT 0x1e

#define regICP_ICP_QGIC2_GICD_ICFGR3 0xc0c  /*register offset*/
#define ICP_ICP_QGIC2_GICD_ICFGR3_INT0_MASK 0x3
#define ICP_ICP_QGIC2_GICD_ICFGR3_INT0_SHIFT 0x0
#define ICP_ICP_QGIC2_GICD_ICFGR3_INT1_MASK 0xc
#define ICP_ICP_QGIC2_GICD_ICFGR3_INT1_SHIFT 0x2
#define ICP_ICP_QGIC2_GICD_ICFGR3_INT2_MASK 0x30
#define ICP_ICP_QGIC2_GICD_ICFGR3_INT2_SHIFT 0x4
#define ICP_ICP_QGIC2_GICD_ICFGR3_INT3_MASK 0xc0
#define ICP_ICP_QGIC2_GICD_ICFGR3_INT3_SHIFT 0x6
#define ICP_ICP_QGIC2_GICD_ICFGR3_INT4_MASK 0x300
#define ICP_ICP_QGIC2_GICD_ICFGR3_INT4_SHIFT 0x8
#define ICP_ICP_QGIC2_GICD_ICFGR3_INT5_MASK 0xc00
#define ICP_ICP_QGIC2_GICD_ICFGR3_INT5_SHIFT 0xa
#define ICP_ICP_QGIC2_GICD_ICFGR3_INT6_MASK 0x3000
#define ICP_ICP_QGIC2_GICD_ICFGR3_INT6_SHIFT 0xc
#define ICP_ICP_QGIC2_GICD_ICFGR3_INT7_MASK 0xc000
#define ICP_ICP_QGIC2_GICD_ICFGR3_INT7_SHIFT 0xe
#define ICP_ICP_QGIC2_GICD_ICFGR3_INT8_MASK 0x30000
#define ICP_ICP_QGIC2_GICD_ICFGR3_INT8_SHIFT 0x10
#define ICP_ICP_QGIC2_GICD_ICFGR3_INT9_MASK 0xc0000
#define ICP_ICP_QGIC2_GICD_ICFGR3_INT9_SHIFT 0x12
#define ICP_ICP_QGIC2_GICD_ICFGR3_INT10_MASK 0x300000
#define ICP_ICP_QGIC2_GICD_ICFGR3_INT10_SHIFT 0x14
#define ICP_ICP_QGIC2_GICD_ICFGR3_INT11_MASK 0xc00000
#define ICP_ICP_QGIC2_GICD_ICFGR3_INT11_SHIFT 0x16
#define ICP_ICP_QGIC2_GICD_ICFGR3_INT12_MASK 0x3000000
#define ICP_ICP_QGIC2_GICD_ICFGR3_INT12_SHIFT 0x18
#define ICP_ICP_QGIC2_GICD_ICFGR3_INT13_MASK 0xc000000
#define ICP_ICP_QGIC2_GICD_ICFGR3_INT13_SHIFT 0x1a
#define ICP_ICP_QGIC2_GICD_ICFGR3_INT14_MASK 0x30000000
#define ICP_ICP_QGIC2_GICD_ICFGR3_INT14_SHIFT 0x1c
#define ICP_ICP_QGIC2_GICD_ICFGR3_INT15_MASK 0xc0000000
#define ICP_ICP_QGIC2_GICD_ICFGR3_INT15_SHIFT 0x1e

#define regICP_ICP_QGIC2_GICD_ICFGR4 0xc10  /*register offset*/
#define ICP_ICP_QGIC2_GICD_ICFGR4_INT0_MASK 0x3
#define ICP_ICP_QGIC2_GICD_ICFGR4_INT0_SHIFT 0x0
#define ICP_ICP_QGIC2_GICD_ICFGR4_INT1_MASK 0xc
#define ICP_ICP_QGIC2_GICD_ICFGR4_INT1_SHIFT 0x2
#define ICP_ICP_QGIC2_GICD_ICFGR4_INT2_MASK 0x30
#define ICP_ICP_QGIC2_GICD_ICFGR4_INT2_SHIFT 0x4
#define ICP_ICP_QGIC2_GICD_ICFGR4_INT3_MASK 0xc0
#define ICP_ICP_QGIC2_GICD_ICFGR4_INT3_SHIFT 0x6
#define ICP_ICP_QGIC2_GICD_ICFGR4_INT4_MASK 0x300
#define ICP_ICP_QGIC2_GICD_ICFGR4_INT4_SHIFT 0x8
#define ICP_ICP_QGIC2_GICD_ICFGR4_INT5_MASK 0xc00
#define ICP_ICP_QGIC2_GICD_ICFGR4_INT5_SHIFT 0xa
#define ICP_ICP_QGIC2_GICD_ICFGR4_INT6_MASK 0x3000
#define ICP_ICP_QGIC2_GICD_ICFGR4_INT6_SHIFT 0xc
#define ICP_ICP_QGIC2_GICD_ICFGR4_INT7_MASK 0xc000
#define ICP_ICP_QGIC2_GICD_ICFGR4_INT7_SHIFT 0xe
#define ICP_ICP_QGIC2_GICD_ICFGR4_INT8_MASK 0x30000
#define ICP_ICP_QGIC2_GICD_ICFGR4_INT8_SHIFT 0x10
#define ICP_ICP_QGIC2_GICD_ICFGR4_INT9_MASK 0xc0000
#define ICP_ICP_QGIC2_GICD_ICFGR4_INT9_SHIFT 0x12
#define ICP_ICP_QGIC2_GICD_ICFGR4_INT10_MASK 0x300000
#define ICP_ICP_QGIC2_GICD_ICFGR4_INT10_SHIFT 0x14
#define ICP_ICP_QGIC2_GICD_ICFGR4_INT11_MASK 0xc00000
#define ICP_ICP_QGIC2_GICD_ICFGR4_INT11_SHIFT 0x16
#define ICP_ICP_QGIC2_GICD_ICFGR4_INT12_MASK 0x3000000
#define ICP_ICP_QGIC2_GICD_ICFGR4_INT12_SHIFT 0x18
#define ICP_ICP_QGIC2_GICD_ICFGR4_INT13_MASK 0xc000000
#define ICP_ICP_QGIC2_GICD_ICFGR4_INT13_SHIFT 0x1a
#define ICP_ICP_QGIC2_GICD_ICFGR4_INT14_MASK 0x30000000
#define ICP_ICP_QGIC2_GICD_ICFGR4_INT14_SHIFT 0x1c
#define ICP_ICP_QGIC2_GICD_ICFGR4_INT15_MASK 0xc0000000
#define ICP_ICP_QGIC2_GICD_ICFGR4_INT15_SHIFT 0x1e

#define regICP_ICP_QGIC2_GICD_ICFGR5 0xc14  /*register offset*/
#define ICP_ICP_QGIC2_GICD_ICFGR5_INT0_MASK 0x3
#define ICP_ICP_QGIC2_GICD_ICFGR5_INT0_SHIFT 0x0
#define ICP_ICP_QGIC2_GICD_ICFGR5_INT1_MASK 0xc
#define ICP_ICP_QGIC2_GICD_ICFGR5_INT1_SHIFT 0x2
#define ICP_ICP_QGIC2_GICD_ICFGR5_INT2_MASK 0x30
#define ICP_ICP_QGIC2_GICD_ICFGR5_INT2_SHIFT 0x4
#define ICP_ICP_QGIC2_GICD_ICFGR5_INT3_MASK 0xc0
#define ICP_ICP_QGIC2_GICD_ICFGR5_INT3_SHIFT 0x6
#define ICP_ICP_QGIC2_GICD_ICFGR5_INT4_MASK 0x300
#define ICP_ICP_QGIC2_GICD_ICFGR5_INT4_SHIFT 0x8
#define ICP_ICP_QGIC2_GICD_ICFGR5_INT5_MASK 0xc00
#define ICP_ICP_QGIC2_GICD_ICFGR5_INT5_SHIFT 0xa
#define ICP_ICP_QGIC2_GICD_ICFGR5_INT6_MASK 0x3000
#define ICP_ICP_QGIC2_GICD_ICFGR5_INT6_SHIFT 0xc
#define ICP_ICP_QGIC2_GICD_ICFGR5_INT7_MASK 0xc000
#define ICP_ICP_QGIC2_GICD_ICFGR5_INT7_SHIFT 0xe
#define ICP_ICP_QGIC2_GICD_ICFGR5_INT8_MASK 0x30000
#define ICP_ICP_QGIC2_GICD_ICFGR5_INT8_SHIFT 0x10
#define ICP_ICP_QGIC2_GICD_ICFGR5_INT9_MASK 0xc0000
#define ICP_ICP_QGIC2_GICD_ICFGR5_INT9_SHIFT 0x12
#define ICP_ICP_QGIC2_GICD_ICFGR5_INT10_MASK 0x300000
#define ICP_ICP_QGIC2_GICD_ICFGR5_INT10_SHIFT 0x14
#define ICP_ICP_QGIC2_GICD_ICFGR5_INT11_MASK 0xc00000
#define ICP_ICP_QGIC2_GICD_ICFGR5_INT11_SHIFT 0x16
#define ICP_ICP_QGIC2_GICD_ICFGR5_INT12_MASK 0x3000000
#define ICP_ICP_QGIC2_GICD_ICFGR5_INT12_SHIFT 0x18
#define ICP_ICP_QGIC2_GICD_ICFGR5_INT13_MASK 0xc000000
#define ICP_ICP_QGIC2_GICD_ICFGR5_INT13_SHIFT 0x1a
#define ICP_ICP_QGIC2_GICD_ICFGR5_INT14_MASK 0x30000000
#define ICP_ICP_QGIC2_GICD_ICFGR5_INT14_SHIFT 0x1c
#define ICP_ICP_QGIC2_GICD_ICFGR5_INT15_MASK 0xc0000000
#define ICP_ICP_QGIC2_GICD_ICFGR5_INT15_SHIFT 0x1e

#define regICP_ICP_QGIC2_GICD_SGIR 0xf00  /*register offset*/
#define ICP_ICP_QGIC2_GICD_SGIR_INT_ID_MASK 0xf
#define ICP_ICP_QGIC2_GICD_SGIR_INT_ID_SHIFT 0x0
#define ICP_ICP_QGIC2_GICD_SGIR_UNUSED0_MASK 0x7ff0
#define ICP_ICP_QGIC2_GICD_SGIR_UNUSED0_SHIFT 0x4
#define ICP_ICP_QGIC2_GICD_SGIR_SATT_MASK 0x8000
#define ICP_ICP_QGIC2_GICD_SGIR_SATT_SHIFT 0xf
#define ICP_ICP_QGIC2_GICD_SGIR_T_LIST_MASK 0xff0000
#define ICP_ICP_QGIC2_GICD_SGIR_T_LIST_SHIFT 0x10
#define ICP_ICP_QGIC2_GICD_SGIR_T_FILTER_MASK 0x3000000
#define ICP_ICP_QGIC2_GICD_SGIR_T_FILTER_SHIFT 0x18
#define ICP_ICP_QGIC2_GICD_SGIR_UNUSED1_MASK 0xfc000000
#define ICP_ICP_QGIC2_GICD_SGIR_UNUSED1_SHIFT 0x1a

#define regICP_ICP_QGIC2_GICD_CPENDSGIR0 0xf10  /*register offset*/
#define ICP_ICP_QGIC2_GICD_CPENDSGIR0_SGI0_MASK 0xff
#define ICP_ICP_QGIC2_GICD_CPENDSGIR0_SGI0_SHIFT 0x0
#define ICP_ICP_QGIC2_GICD_CPENDSGIR0_SGI1_MASK 0xff00
#define ICP_ICP_QGIC2_GICD_CPENDSGIR0_SGI1_SHIFT 0x8
#define ICP_ICP_QGIC2_GICD_CPENDSGIR0_SGI2_MASK 0xff0000
#define ICP_ICP_QGIC2_GICD_CPENDSGIR0_SGI2_SHIFT 0x10
#define ICP_ICP_QGIC2_GICD_CPENDSGIR0_SGI3_MASK 0xff000000
#define ICP_ICP_QGIC2_GICD_CPENDSGIR0_SGI3_SHIFT 0x18

#define regICP_ICP_QGIC2_GICD_CPENDSGIR1 0xf14  /*register offset*/
#define ICP_ICP_QGIC2_GICD_CPENDSGIR1_SGI0_MASK 0xff
#define ICP_ICP_QGIC2_GICD_CPENDSGIR1_SGI0_SHIFT 0x0
#define ICP_ICP_QGIC2_GICD_CPENDSGIR1_SGI1_MASK 0xff00
#define ICP_ICP_QGIC2_GICD_CPENDSGIR1_SGI1_SHIFT 0x8
#define ICP_ICP_QGIC2_GICD_CPENDSGIR1_SGI2_MASK 0xff0000
#define ICP_ICP_QGIC2_GICD_CPENDSGIR1_SGI2_SHIFT 0x10
#define ICP_ICP_QGIC2_GICD_CPENDSGIR1_SGI3_MASK 0xff000000
#define ICP_ICP_QGIC2_GICD_CPENDSGIR1_SGI3_SHIFT 0x18

#define regICP_ICP_QGIC2_GICD_CPENDSGIR2 0xf18  /*register offset*/
#define ICP_ICP_QGIC2_GICD_CPENDSGIR2_SGI0_MASK 0xff
#define ICP_ICP_QGIC2_GICD_CPENDSGIR2_SGI0_SHIFT 0x0
#define ICP_ICP_QGIC2_GICD_CPENDSGIR2_SGI1_MASK 0xff00
#define ICP_ICP_QGIC2_GICD_CPENDSGIR2_SGI1_SHIFT 0x8
#define ICP_ICP_QGIC2_GICD_CPENDSGIR2_SGI2_MASK 0xff0000
#define ICP_ICP_QGIC2_GICD_CPENDSGIR2_SGI2_SHIFT 0x10
#define ICP_ICP_QGIC2_GICD_CPENDSGIR2_SGI3_MASK 0xff000000
#define ICP_ICP_QGIC2_GICD_CPENDSGIR2_SGI3_SHIFT 0x18

#define regICP_ICP_QGIC2_GICD_CPENDSGIR3 0xf1c  /*register offset*/
#define ICP_ICP_QGIC2_GICD_CPENDSGIR3_SGI0_MASK 0xff
#define ICP_ICP_QGIC2_GICD_CPENDSGIR3_SGI0_SHIFT 0x0
#define ICP_ICP_QGIC2_GICD_CPENDSGIR3_SGI1_MASK 0xff00
#define ICP_ICP_QGIC2_GICD_CPENDSGIR3_SGI1_SHIFT 0x8
#define ICP_ICP_QGIC2_GICD_CPENDSGIR3_SGI2_MASK 0xff0000
#define ICP_ICP_QGIC2_GICD_CPENDSGIR3_SGI2_SHIFT 0x10
#define ICP_ICP_QGIC2_GICD_CPENDSGIR3_SGI3_MASK 0xff000000
#define ICP_ICP_QGIC2_GICD_CPENDSGIR3_SGI3_SHIFT 0x18

#define regICP_ICP_QGIC2_GICD_SPENDSGIR0 0xf20  /*register offset*/
#define ICP_ICP_QGIC2_GICD_SPENDSGIR0_SGI0_MASK 0xff
#define ICP_ICP_QGIC2_GICD_SPENDSGIR0_SGI0_SHIFT 0x0
#define ICP_ICP_QGIC2_GICD_SPENDSGIR0_SGI1_MASK 0xff00
#define ICP_ICP_QGIC2_GICD_SPENDSGIR0_SGI1_SHIFT 0x8
#define ICP_ICP_QGIC2_GICD_SPENDSGIR0_SGI2_MASK 0xff0000
#define ICP_ICP_QGIC2_GICD_SPENDSGIR0_SGI2_SHIFT 0x10
#define ICP_ICP_QGIC2_GICD_SPENDSGIR0_SGI3_MASK 0xff000000
#define ICP_ICP_QGIC2_GICD_SPENDSGIR0_SGI3_SHIFT 0x18

#define regICP_ICP_QGIC2_GICD_SPENDSGIR1 0xf24  /*register offset*/
#define ICP_ICP_QGIC2_GICD_SPENDSGIR1_SGI0_MASK 0xff
#define ICP_ICP_QGIC2_GICD_SPENDSGIR1_SGI0_SHIFT 0x0
#define ICP_ICP_QGIC2_GICD_SPENDSGIR1_SGI1_MASK 0xff00
#define ICP_ICP_QGIC2_GICD_SPENDSGIR1_SGI1_SHIFT 0x8
#define ICP_ICP_QGIC2_GICD_SPENDSGIR1_SGI2_MASK 0xff0000
#define ICP_ICP_QGIC2_GICD_SPENDSGIR1_SGI2_SHIFT 0x10
#define ICP_ICP_QGIC2_GICD_SPENDSGIR1_SGI3_MASK 0xff000000
#define ICP_ICP_QGIC2_GICD_SPENDSGIR1_SGI3_SHIFT 0x18

#define regICP_ICP_QGIC2_GICD_SPENDSGIR2 0xf28  /*register offset*/
#define ICP_ICP_QGIC2_GICD_SPENDSGIR2_SGI0_MASK 0xff
#define ICP_ICP_QGIC2_GICD_SPENDSGIR2_SGI0_SHIFT 0x0
#define ICP_ICP_QGIC2_GICD_SPENDSGIR2_SGI1_MASK 0xff00
#define ICP_ICP_QGIC2_GICD_SPENDSGIR2_SGI1_SHIFT 0x8
#define ICP_ICP_QGIC2_GICD_SPENDSGIR2_SGI2_MASK 0xff0000
#define ICP_ICP_QGIC2_GICD_SPENDSGIR2_SGI2_SHIFT 0x10
#define ICP_ICP_QGIC2_GICD_SPENDSGIR2_SGI3_MASK 0xff000000
#define ICP_ICP_QGIC2_GICD_SPENDSGIR2_SGI3_SHIFT 0x18

#define regICP_ICP_QGIC2_GICD_SPENDSGIR3 0xf2c  /*register offset*/
#define ICP_ICP_QGIC2_GICD_SPENDSGIR3_SGI0_MASK 0xff
#define ICP_ICP_QGIC2_GICD_SPENDSGIR3_SGI0_SHIFT 0x0
#define ICP_ICP_QGIC2_GICD_SPENDSGIR3_SGI1_MASK 0xff00
#define ICP_ICP_QGIC2_GICD_SPENDSGIR3_SGI1_SHIFT 0x8
#define ICP_ICP_QGIC2_GICD_SPENDSGIR3_SGI2_MASK 0xff0000
#define ICP_ICP_QGIC2_GICD_SPENDSGIR3_SGI2_SHIFT 0x10
#define ICP_ICP_QGIC2_GICD_SPENDSGIR3_SGI3_MASK 0xff000000
#define ICP_ICP_QGIC2_GICD_SPENDSGIR3_SGI3_SHIFT 0x18

#define regICP_ICP_QGIC2_GICD_PIDR0 0xfd0  /*register offset*/
#define ICP_ICP_QGIC2_GICD_PIDR0_PART_NUM_MASK 0xff
#define ICP_ICP_QGIC2_GICD_PIDR0_PART_NUM_SHIFT 0x0
#define ICP_ICP_QGIC2_GICD_PIDR0_UNUSED0_MASK 0xffffff00
#define ICP_ICP_QGIC2_GICD_PIDR0_UNUSED0_SHIFT 0x8

#define regICP_ICP_QGIC2_GICD_PIDR1 0xfd4  /*register offset*/
#define ICP_ICP_QGIC2_GICD_PIDR1_PART_NUM_MASK 0xf
#define ICP_ICP_QGIC2_GICD_PIDR1_PART_NUM_SHIFT 0x0
#define ICP_ICP_QGIC2_GICD_PIDR1_DESIGNER_MASK 0xf0
#define ICP_ICP_QGIC2_GICD_PIDR1_DESIGNER_SHIFT 0x4
#define ICP_ICP_QGIC2_GICD_PIDR1_UNUSED0_MASK 0xffffff00
#define ICP_ICP_QGIC2_GICD_PIDR1_UNUSED0_SHIFT 0x8

#define regICP_ICP_QGIC2_GICD_PIDR2 0xfd8  /*register offset*/
#define ICP_ICP_QGIC2_GICD_PIDR2_DESIGNER_MASK 0x7
#define ICP_ICP_QGIC2_GICD_PIDR2_DESIGNER_SHIFT 0x0
#define ICP_ICP_QGIC2_GICD_PIDR2_USES_JEP_CODE_MASK 0x8
#define ICP_ICP_QGIC2_GICD_PIDR2_USES_JEP_CODE_SHIFT 0x3
#define ICP_ICP_QGIC2_GICD_PIDR2_ARCH_VERSION_MASK 0xf0
#define ICP_ICP_QGIC2_GICD_PIDR2_ARCH_VERSION_SHIFT 0x4
#define ICP_ICP_QGIC2_GICD_PIDR2_UNUSED0_MASK 0xffffff00
#define ICP_ICP_QGIC2_GICD_PIDR2_UNUSED0_SHIFT 0x8

#define regICP_ICP_QGIC2_GICD_PIDR3 0xfdc  /*register offset*/
#define ICP_ICP_QGIC2_GICD_PIDR3_UNUSED0_MASK 0xf
#define ICP_ICP_QGIC2_GICD_PIDR3_UNUSED0_SHIFT 0x0
#define ICP_ICP_QGIC2_GICD_PIDR3_REVISION_MASK 0xf0
#define ICP_ICP_QGIC2_GICD_PIDR3_REVISION_SHIFT 0x4
#define ICP_ICP_QGIC2_GICD_PIDR3_UNUSED1_MASK 0xffffff00
#define ICP_ICP_QGIC2_GICD_PIDR3_UNUSED1_SHIFT 0x8

#define regICP_ICP_QGIC2_GICD_PIDR4 0xfe0  /*register offset*/
#define ICP_ICP_QGIC2_GICD_PIDR4_DESIGNER_MASK 0xf
#define ICP_ICP_QGIC2_GICD_PIDR4_DESIGNER_SHIFT 0x0
#define ICP_ICP_QGIC2_GICD_PIDR4_UNUSED0_MASK 0xfffffff0
#define ICP_ICP_QGIC2_GICD_PIDR4_UNUSED0_SHIFT 0x4

#define regICP_ICP_QGIC2_GICD_PIDR5 0xfe4  /*register offset*/
#define ICP_ICP_QGIC2_GICD_PIDR5_RESRVD_BY_ARM_MASK 0xff
#define ICP_ICP_QGIC2_GICD_PIDR5_RESRVD_BY_ARM_SHIFT 0x0
#define ICP_ICP_QGIC2_GICD_PIDR5_UNUSED0_MASK 0xffffff00
#define ICP_ICP_QGIC2_GICD_PIDR5_UNUSED0_SHIFT 0x8

#define regICP_ICP_QGIC2_GICD_PIDR6 0xfe8  /*register offset*/
#define ICP_ICP_QGIC2_GICD_PIDR6_RESRVD_BY_ARM_MASK 0xff
#define ICP_ICP_QGIC2_GICD_PIDR6_RESRVD_BY_ARM_SHIFT 0x0
#define ICP_ICP_QGIC2_GICD_PIDR6_UNUSED0_MASK 0xffffff00
#define ICP_ICP_QGIC2_GICD_PIDR6_UNUSED0_SHIFT 0x8

#define regICP_ICP_QGIC2_GICD_PIDR7 0xfec  /*register offset*/
#define ICP_ICP_QGIC2_GICD_PIDR7_RESRVD_BY_ARM_MASK 0xff
#define ICP_ICP_QGIC2_GICD_PIDR7_RESRVD_BY_ARM_SHIFT 0x0
#define ICP_ICP_QGIC2_GICD_PIDR7_UNUSED0_MASK 0xffffff00
#define ICP_ICP_QGIC2_GICD_PIDR7_UNUSED0_SHIFT 0x8

#define regICP_ICP_QGIC2_GICD_CIDR0 0xff0  /*register offset*/
#define ICP_ICP_QGIC2_GICD_CIDR0_COMP_ID_0_MASK 0xff
#define ICP_ICP_QGIC2_GICD_CIDR0_COMP_ID_0_SHIFT 0x0
#define ICP_ICP_QGIC2_GICD_CIDR0_UNUSED0_MASK 0xffffff00
#define ICP_ICP_QGIC2_GICD_CIDR0_UNUSED0_SHIFT 0x8

#define regICP_ICP_QGIC2_GICD_CIDR1 0xff4  /*register offset*/
#define ICP_ICP_QGIC2_GICD_CIDR1_COMP_ID_1_MASK 0xff
#define ICP_ICP_QGIC2_GICD_CIDR1_COMP_ID_1_SHIFT 0x0
#define ICP_ICP_QGIC2_GICD_CIDR1_UNUSED0_MASK 0xffffff00
#define ICP_ICP_QGIC2_GICD_CIDR1_UNUSED0_SHIFT 0x8

#define regICP_ICP_QGIC2_GICD_CIDR2 0xff8  /*register offset*/
#define ICP_ICP_QGIC2_GICD_CIDR2_COMP_ID_2_MASK 0xff
#define ICP_ICP_QGIC2_GICD_CIDR2_COMP_ID_2_SHIFT 0x0
#define ICP_ICP_QGIC2_GICD_CIDR2_UNUSED0_MASK 0xffffff00
#define ICP_ICP_QGIC2_GICD_CIDR2_UNUSED0_SHIFT 0x8

#define regICP_ICP_QGIC2_GICD_CIDR3 0xffc  /*register offset*/
#define ICP_ICP_QGIC2_GICD_CIDR3_COMP_ID_3_MASK 0xff
#define ICP_ICP_QGIC2_GICD_CIDR3_COMP_ID_3_SHIFT 0x0
#define ICP_ICP_QGIC2_GICD_CIDR3_UNUSED0_MASK 0xffffff00
#define ICP_ICP_QGIC2_GICD_CIDR3_UNUSED0_SHIFT 0x8

#define regICP_ICP_QGIC2_GICH_HCR 0x1000  /*register offset*/
#define ICP_ICP_QGIC2_GICH_HCR_EN_MASK 0x1
#define ICP_ICP_QGIC2_GICH_HCR_EN_SHIFT 0x0
#define ICP_ICP_QGIC2_GICH_HCR_UIE_MASK 0x2
#define ICP_ICP_QGIC2_GICH_HCR_UIE_SHIFT 0x1
#define ICP_ICP_QGIC2_GICH_HCR_SKIDIE_MASK 0x4
#define ICP_ICP_QGIC2_GICH_HCR_SKIDIE_SHIFT 0x2
#define ICP_ICP_QGIC2_GICH_HCR_NPIE_MASK 0x8
#define ICP_ICP_QGIC2_GICH_HCR_NPIE_SHIFT 0x3
#define ICP_ICP_QGIC2_GICH_HCR_VEG0IE_MASK 0x10
#define ICP_ICP_QGIC2_GICH_HCR_VEG0IE_SHIFT 0x4
#define ICP_ICP_QGIC2_GICH_HCR_VDG0IE_MASK 0x20
#define ICP_ICP_QGIC2_GICH_HCR_VDG0IE_SHIFT 0x5
#define ICP_ICP_QGIC2_GICH_HCR_VEG1IE_MASK 0x40
#define ICP_ICP_QGIC2_GICH_HCR_VEG1IE_SHIFT 0x6
#define ICP_ICP_QGIC2_GICH_HCR_VDG1IE_MASK 0x80
#define ICP_ICP_QGIC2_GICH_HCR_VDG1IE_SHIFT 0x7
#define ICP_ICP_QGIC2_GICH_HCR_UNUSED0_MASK 0x7ffff00
#define ICP_ICP_QGIC2_GICH_HCR_UNUSED0_SHIFT 0x8
#define ICP_ICP_QGIC2_GICH_HCR_EOICOUNT_MASK 0xf8000000
#define ICP_ICP_QGIC2_GICH_HCR_EOICOUNT_SHIFT 0x1b

#define regICP_ICP_QGIC2_GICH_VTR 0x1004  /*register offset*/
#define ICP_ICP_QGIC2_GICH_VTR_LISTREGS_MASK 0x3f
#define ICP_ICP_QGIC2_GICH_VTR_LISTREGS_SHIFT 0x0
#define ICP_ICP_QGIC2_GICH_VTR_UNUSED0_MASK 0x3ffffc0
#define ICP_ICP_QGIC2_GICH_VTR_UNUSED0_SHIFT 0x6
#define ICP_ICP_QGIC2_GICH_VTR_PREBITS_MASK 0x1c000000
#define ICP_ICP_QGIC2_GICH_VTR_PREBITS_SHIFT 0x1a
#define ICP_ICP_QGIC2_GICH_VTR_PRIBITS_MASK 0xe0000000
#define ICP_ICP_QGIC2_GICH_VTR_PRIBITS_SHIFT 0x1d

#define regICP_ICP_QGIC2_GICH_VMCR 0x1008  /*register offset*/
#define ICP_ICP_QGIC2_GICH_VMCR_VMENABLE_G0_MASK 0x1
#define ICP_ICP_QGIC2_GICH_VMCR_VMENABLE_G0_SHIFT 0x0
#define ICP_ICP_QGIC2_GICH_VMCR_VMENABLE_G1_MASK 0x2
#define ICP_ICP_QGIC2_GICH_VMCR_VMENABLE_G1_SHIFT 0x1
#define ICP_ICP_QGIC2_GICH_VMCR_VMACKCTL_MASK 0x4
#define ICP_ICP_QGIC2_GICH_VMCR_VMACKCTL_SHIFT 0x2
#define ICP_ICP_QGIC2_GICH_VMCR_VMFIQEN_MASK 0x8
#define ICP_ICP_QGIC2_GICH_VMCR_VMFIQEN_SHIFT 0x3
#define ICP_ICP_QGIC2_GICH_VMCR_VMGBPR_MASK 0x10
#define ICP_ICP_QGIC2_GICH_VMCR_VMGBPR_SHIFT 0x4
#define ICP_ICP_QGIC2_GICH_VMCR_UNUSED0_MASK 0x1e0
#define ICP_ICP_QGIC2_GICH_VMCR_UNUSED0_SHIFT 0x5
#define ICP_ICP_QGIC2_GICH_VMCR_VEM_MASK 0x200
#define ICP_ICP_QGIC2_GICH_VMCR_VEM_SHIFT 0x9
#define ICP_ICP_QGIC2_GICH_VMCR_UNUSED1_MASK 0x3fc00
#define ICP_ICP_QGIC2_GICH_VMCR_UNUSED1_SHIFT 0xa
#define ICP_ICP_QGIC2_GICH_VMCR_VMG1BP_MASK 0x1c0000
#define ICP_ICP_QGIC2_GICH_VMCR_VMG1BP_SHIFT 0x12
#define ICP_ICP_QGIC2_GICH_VMCR_VMG0BP_MASK 0xe00000
#define ICP_ICP_QGIC2_GICH_VMCR_VMG0BP_SHIFT 0x15
#define ICP_ICP_QGIC2_GICH_VMCR_UNUSED2_MASK 0x7000000
#define ICP_ICP_QGIC2_GICH_VMCR_UNUSED2_SHIFT 0x18
#define ICP_ICP_QGIC2_GICH_VMCR_VMPMR_MASK 0xf8000000
#define ICP_ICP_QGIC2_GICH_VMCR_VMPMR_SHIFT 0x1b

#define regICP_ICP_QGIC2_GICH_MISR 0x1010  /*register offset*/
#define ICP_ICP_QGIC2_GICH_MISR_EI_MASK 0x1
#define ICP_ICP_QGIC2_GICH_MISR_EI_SHIFT 0x0
#define ICP_ICP_QGIC2_GICH_MISR_UI_MASK 0x2
#define ICP_ICP_QGIC2_GICH_MISR_UI_SHIFT 0x1
#define ICP_ICP_QGIC2_GICH_MISR_SKIDI_MASK 0x4
#define ICP_ICP_QGIC2_GICH_MISR_SKIDI_SHIFT 0x2
#define ICP_ICP_QGIC2_GICH_MISR_NPI_MASK 0x8
#define ICP_ICP_QGIC2_GICH_MISR_NPI_SHIFT 0x3
#define ICP_ICP_QGIC2_GICH_MISR_VESI_MASK 0x10
#define ICP_ICP_QGIC2_GICH_MISR_VESI_SHIFT 0x4
#define ICP_ICP_QGIC2_GICH_MISR_VDSI_MASK 0x20
#define ICP_ICP_QGIC2_GICH_MISR_VDSI_SHIFT 0x5
#define ICP_ICP_QGIC2_GICH_MISR_VENSI_MASK 0x40
#define ICP_ICP_QGIC2_GICH_MISR_VENSI_SHIFT 0x6
#define ICP_ICP_QGIC2_GICH_MISR_VDNSI_MASK 0x80
#define ICP_ICP_QGIC2_GICH_MISR_VDNSI_SHIFT 0x7
#define ICP_ICP_QGIC2_GICH_MISR_UNUSED0_MASK 0xffffff00
#define ICP_ICP_QGIC2_GICH_MISR_UNUSED0_SHIFT 0x8

#define regICP_ICP_QGIC2_GICH_EISR 0x1020  /*register offset*/
#define ICP_ICP_QGIC2_GICH_EISR_LR_MASK 0xf
#define ICP_ICP_QGIC2_GICH_EISR_LR_SHIFT 0x0
#define ICP_ICP_QGIC2_GICH_EISR_UNUSED0_MASK 0xfffffff0
#define ICP_ICP_QGIC2_GICH_EISR_UNUSED0_SHIFT 0x4

#define regICP_ICP_QGIC2_GICH_ELRSR 0x1030  /*register offset*/
#define ICP_ICP_QGIC2_GICH_ELRSR_LR_MASK 0xf
#define ICP_ICP_QGIC2_GICH_ELRSR_LR_SHIFT 0x0
#define ICP_ICP_QGIC2_GICH_ELRSR_UNUSED0_MASK 0xfffffff0
#define ICP_ICP_QGIC2_GICH_ELRSR_UNUSED0_SHIFT 0x4

#define regICP_ICP_QGIC2_GICH_APR 0x10f0  /*register offset*/
#define ICP_ICP_QGIC2_GICH_APR_PRI_MASK 0xffffffff
#define ICP_ICP_QGIC2_GICH_APR_PRI_SHIFT 0x0

#define regICP_ICP_QGIC2_GICH_LR0 0x1100  /*register offset*/
#define ICP_ICP_QGIC2_GICH_LR0_VIRTL_ID_MASK 0x3ff
#define ICP_ICP_QGIC2_GICH_LR0_VIRTL_ID_SHIFT 0x0
#define ICP_ICP_QGIC2_GICH_LR0_PHY_ID_MASK 0xffc00
#define ICP_ICP_QGIC2_GICH_LR0_PHY_ID_SHIFT 0xa
#define ICP_ICP_QGIC2_GICH_LR0_UNUSED0_MASK 0x700000
#define ICP_ICP_QGIC2_GICH_LR0_UNUSED0_SHIFT 0x14
#define ICP_ICP_QGIC2_GICH_LR0_PRI_MASK 0xf800000
#define ICP_ICP_QGIC2_GICH_LR0_PRI_SHIFT 0x17
#define ICP_ICP_QGIC2_GICH_LR0_STATE_MASK 0x30000000
#define ICP_ICP_QGIC2_GICH_LR0_STATE_SHIFT 0x1c
#define ICP_ICP_QGIC2_GICH_LR0_GRP_MASK 0x40000000
#define ICP_ICP_QGIC2_GICH_LR0_GRP_SHIFT 0x1e
#define ICP_ICP_QGIC2_GICH_LR0_HW_MASK 0x80000000
#define ICP_ICP_QGIC2_GICH_LR0_HW_SHIFT 0x1f

#define regICP_ICP_QGIC2_GICH_LR1 0x1104  /*register offset*/
#define ICP_ICP_QGIC2_GICH_LR1_VIRTL_ID_MASK 0x3ff
#define ICP_ICP_QGIC2_GICH_LR1_VIRTL_ID_SHIFT 0x0
#define ICP_ICP_QGIC2_GICH_LR1_PHY_ID_MASK 0xffc00
#define ICP_ICP_QGIC2_GICH_LR1_PHY_ID_SHIFT 0xa
#define ICP_ICP_QGIC2_GICH_LR1_UNUSED0_MASK 0x700000
#define ICP_ICP_QGIC2_GICH_LR1_UNUSED0_SHIFT 0x14
#define ICP_ICP_QGIC2_GICH_LR1_PRI_MASK 0xf800000
#define ICP_ICP_QGIC2_GICH_LR1_PRI_SHIFT 0x17
#define ICP_ICP_QGIC2_GICH_LR1_STATE_MASK 0x30000000
#define ICP_ICP_QGIC2_GICH_LR1_STATE_SHIFT 0x1c
#define ICP_ICP_QGIC2_GICH_LR1_GRP_MASK 0x40000000
#define ICP_ICP_QGIC2_GICH_LR1_GRP_SHIFT 0x1e
#define ICP_ICP_QGIC2_GICH_LR1_HW_MASK 0x80000000
#define ICP_ICP_QGIC2_GICH_LR1_HW_SHIFT 0x1f

#define regICP_ICP_QGIC2_GICH_LR2 0x1108  /*register offset*/
#define ICP_ICP_QGIC2_GICH_LR2_VIRTL_ID_MASK 0x3ff
#define ICP_ICP_QGIC2_GICH_LR2_VIRTL_ID_SHIFT 0x0
#define ICP_ICP_QGIC2_GICH_LR2_PHY_ID_MASK 0xffc00
#define ICP_ICP_QGIC2_GICH_LR2_PHY_ID_SHIFT 0xa
#define ICP_ICP_QGIC2_GICH_LR2_UNUSED0_MASK 0x700000
#define ICP_ICP_QGIC2_GICH_LR2_UNUSED0_SHIFT 0x14
#define ICP_ICP_QGIC2_GICH_LR2_PRI_MASK 0xf800000
#define ICP_ICP_QGIC2_GICH_LR2_PRI_SHIFT 0x17
#define ICP_ICP_QGIC2_GICH_LR2_STATE_MASK 0x30000000
#define ICP_ICP_QGIC2_GICH_LR2_STATE_SHIFT 0x1c
#define ICP_ICP_QGIC2_GICH_LR2_GRP_MASK 0x40000000
#define ICP_ICP_QGIC2_GICH_LR2_GRP_SHIFT 0x1e
#define ICP_ICP_QGIC2_GICH_LR2_HW_MASK 0x80000000
#define ICP_ICP_QGIC2_GICH_LR2_HW_SHIFT 0x1f

#define regICP_ICP_QGIC2_GICH_LR3 0x110c  /*register offset*/
#define ICP_ICP_QGIC2_GICH_LR3_VIRTL_ID_MASK 0x3ff
#define ICP_ICP_QGIC2_GICH_LR3_VIRTL_ID_SHIFT 0x0
#define ICP_ICP_QGIC2_GICH_LR3_PHY_ID_MASK 0xffc00
#define ICP_ICP_QGIC2_GICH_LR3_PHY_ID_SHIFT 0xa
#define ICP_ICP_QGIC2_GICH_LR3_UNUSED0_MASK 0x700000
#define ICP_ICP_QGIC2_GICH_LR3_UNUSED0_SHIFT 0x14
#define ICP_ICP_QGIC2_GICH_LR3_PRI_MASK 0xf800000
#define ICP_ICP_QGIC2_GICH_LR3_PRI_SHIFT 0x17
#define ICP_ICP_QGIC2_GICH_LR3_STATE_MASK 0x30000000
#define ICP_ICP_QGIC2_GICH_LR3_STATE_SHIFT 0x1c
#define ICP_ICP_QGIC2_GICH_LR3_GRP_MASK 0x40000000
#define ICP_ICP_QGIC2_GICH_LR3_GRP_SHIFT 0x1e
#define ICP_ICP_QGIC2_GICH_LR3_HW_MASK 0x80000000
#define ICP_ICP_QGIC2_GICH_LR3_HW_SHIFT 0x1f

#define regICP_ICP_QGIC2_GICH_SW_LR 0x1120  /*register offset*/
#define ICP_ICP_QGIC2_GICH_SW_LR_UNUSED0_MASK 0x3ff
#define ICP_ICP_QGIC2_GICH_SW_LR_UNUSED0_SHIFT 0x0
#define ICP_ICP_QGIC2_GICH_SW_LR_CPUID_MASK 0x1c00
#define ICP_ICP_QGIC2_GICH_SW_LR_CPUID_SHIFT 0xa
#define ICP_ICP_QGIC2_GICH_SW_LR_UNUSED1_MASK 0x7e000
#define ICP_ICP_QGIC2_GICH_SW_LR_UNUSED1_SHIFT 0xd
#define ICP_ICP_QGIC2_GICH_SW_LR_EI_MASK 0x80000
#define ICP_ICP_QGIC2_GICH_SW_LR_EI_SHIFT 0x13
#define ICP_ICP_QGIC2_GICH_SW_LR_UNUSED2_MASK 0xfff00000
#define ICP_ICP_QGIC2_GICH_SW_LR_UNUSED2_SHIFT 0x14

#define regICP_ICP_QGIC2_GICC_CTLR 0x2000  /*register offset*/
#define ICP_ICP_QGIC2_GICC_CTLR_ENABLE_MASK 0x1
#define ICP_ICP_QGIC2_GICC_CTLR_ENABLE_SHIFT 0x0
#define ICP_ICP_QGIC2_GICC_CTLR_ENABLE_NS_MASK 0x2
#define ICP_ICP_QGIC2_GICC_CTLR_ENABLE_NS_SHIFT 0x1
#define ICP_ICP_QGIC2_GICC_CTLR_ACKCTL_MASK 0x4
#define ICP_ICP_QGIC2_GICC_CTLR_ACKCTL_SHIFT 0x2
#define ICP_ICP_QGIC2_GICC_CTLR_S_DEST_MASK 0x8
#define ICP_ICP_QGIC2_GICC_CTLR_S_DEST_SHIFT 0x3
#define ICP_ICP_QGIC2_GICC_CTLR_SBPR_MASK 0x10
#define ICP_ICP_QGIC2_GICC_CTLR_SBPR_SHIFT 0x4
#define ICP_ICP_QGIC2_GICC_CTLR_FIQBYPDISABLE_MASK 0x20
#define ICP_ICP_QGIC2_GICC_CTLR_FIQBYPDISABLE_SHIFT 0x5
#define ICP_ICP_QGIC2_GICC_CTLR_IRQBYPDISABLE_MASK 0x40
#define ICP_ICP_QGIC2_GICC_CTLR_IRQBYPDISABLE_SHIFT 0x6
#define ICP_ICP_QGIC2_GICC_CTLR_FIQBYPDISABLENS_MASK 0x80
#define ICP_ICP_QGIC2_GICC_CTLR_FIQBYPDISABLENS_SHIFT 0x7
#define ICP_ICP_QGIC2_GICC_CTLR_IRQBYPDISABLENS_MASK 0x100
#define ICP_ICP_QGIC2_GICC_CTLR_IRQBYPDISABLENS_SHIFT 0x8
#define ICP_ICP_QGIC2_GICC_CTLR_EOIMODE_MASK 0x200
#define ICP_ICP_QGIC2_GICC_CTLR_EOIMODE_SHIFT 0x9
#define ICP_ICP_QGIC2_GICC_CTLR_EOIMODENS_MASK 0x400
#define ICP_ICP_QGIC2_GICC_CTLR_EOIMODENS_SHIFT 0xa
#define ICP_ICP_QGIC2_GICC_CTLR_UNUSED0_MASK 0xfffff800
#define ICP_ICP_QGIC2_GICC_CTLR_UNUSED0_SHIFT 0xb

#define regICP_ICP_QGIC2_GICC_PMR 0x2004  /*register offset*/
#define ICP_ICP_QGIC2_GICC_PMR_UNUSED0_MASK 0x7
#define ICP_ICP_QGIC2_GICC_PMR_UNUSED0_SHIFT 0x0
#define ICP_ICP_QGIC2_GICC_PMR_LEVEL_MASK 0xf8
#define ICP_ICP_QGIC2_GICC_PMR_LEVEL_SHIFT 0x3
#define ICP_ICP_QGIC2_GICC_PMR_UNUSED1_MASK 0xffffff00
#define ICP_ICP_QGIC2_GICC_PMR_UNUSED1_SHIFT 0x8

#define regICP_ICP_QGIC2_GICC_BPR 0x2008  /*register offset*/
#define ICP_ICP_QGIC2_GICC_BPR_VAL_MASK 0x7
#define ICP_ICP_QGIC2_GICC_BPR_VAL_SHIFT 0x0
#define ICP_ICP_QGIC2_GICC_BPR_UNUSED0_MASK 0xfffffff8
#define ICP_ICP_QGIC2_GICC_BPR_UNUSED0_SHIFT 0x3

#define regICP_ICP_QGIC2_GICC_IAR 0x200c  /*register offset*/
#define ICP_ICP_QGIC2_GICC_IAR_INT_ID_MASK 0x3ff
#define ICP_ICP_QGIC2_GICC_IAR_INT_ID_SHIFT 0x0
#define ICP_ICP_QGIC2_GICC_IAR_CPU_ID_MASK 0x1c00
#define ICP_ICP_QGIC2_GICC_IAR_CPU_ID_SHIFT 0xa
#define ICP_ICP_QGIC2_GICC_IAR_UNUSED0_MASK 0xffffe000
#define ICP_ICP_QGIC2_GICC_IAR_UNUSED0_SHIFT 0xd

#define regICP_ICP_QGIC2_GICC_EOIR 0x2010  /*register offset*/
#define ICP_ICP_QGIC2_GICC_EOIR_INT_ID_MASK 0x3ff
#define ICP_ICP_QGIC2_GICC_EOIR_INT_ID_SHIFT 0x0
#define ICP_ICP_QGIC2_GICC_EOIR_CPU_ID_MASK 0x1c00
#define ICP_ICP_QGIC2_GICC_EOIR_CPU_ID_SHIFT 0xa
#define ICP_ICP_QGIC2_GICC_EOIR_UNUSED0_MASK 0xffffe000
#define ICP_ICP_QGIC2_GICC_EOIR_UNUSED0_SHIFT 0xd

#define regICP_ICP_QGIC2_GICC_RPR 0x2014  /*register offset*/
#define ICP_ICP_QGIC2_GICC_RPR_UNUSED0_MASK 0x7
#define ICP_ICP_QGIC2_GICC_RPR_UNUSED0_SHIFT 0x0
#define ICP_ICP_QGIC2_GICC_RPR_VAL_MASK 0xf8
#define ICP_ICP_QGIC2_GICC_RPR_VAL_SHIFT 0x3
#define ICP_ICP_QGIC2_GICC_RPR_UNUSED1_MASK 0xffffff00
#define ICP_ICP_QGIC2_GICC_RPR_UNUSED1_SHIFT 0x8

#define regICP_ICP_QGIC2_GICC_HPPIR 0x2018  /*register offset*/
#define ICP_ICP_QGIC2_GICC_HPPIR_INT_ID_MASK 0x3ff
#define ICP_ICP_QGIC2_GICC_HPPIR_INT_ID_SHIFT 0x0
#define ICP_ICP_QGIC2_GICC_HPPIR_CPU_ID_MASK 0x1c00
#define ICP_ICP_QGIC2_GICC_HPPIR_CPU_ID_SHIFT 0xa
#define ICP_ICP_QGIC2_GICC_HPPIR_UNUSED0_MASK 0xffffe000
#define ICP_ICP_QGIC2_GICC_HPPIR_UNUSED0_SHIFT 0xd

#define regICP_ICP_QGIC2_GICC_ABPR 0x201c  /*register offset*/
#define ICP_ICP_QGIC2_GICC_ABPR_VAL_MASK 0x7
#define ICP_ICP_QGIC2_GICC_ABPR_VAL_SHIFT 0x0
#define ICP_ICP_QGIC2_GICC_ABPR_UNUSED0_MASK 0xfffffff8
#define ICP_ICP_QGIC2_GICC_ABPR_UNUSED0_SHIFT 0x3

#define regICP_ICP_QGIC2_GICC_AIAR 0x2020  /*register offset*/
#define ICP_ICP_QGIC2_GICC_AIAR_INT_ID_MASK 0x3ff
#define ICP_ICP_QGIC2_GICC_AIAR_INT_ID_SHIFT 0x0
#define ICP_ICP_QGIC2_GICC_AIAR_CPU_ID_MASK 0x1c00
#define ICP_ICP_QGIC2_GICC_AIAR_CPU_ID_SHIFT 0xa
#define ICP_ICP_QGIC2_GICC_AIAR_UNUSED0_MASK 0xffffe000
#define ICP_ICP_QGIC2_GICC_AIAR_UNUSED0_SHIFT 0xd

#define regICP_ICP_QGIC2_GICC_AEOIR 0x2024  /*register offset*/
#define ICP_ICP_QGIC2_GICC_AEOIR_INT_ID_MASK 0x3ff
#define ICP_ICP_QGIC2_GICC_AEOIR_INT_ID_SHIFT 0x0
#define ICP_ICP_QGIC2_GICC_AEOIR_CPU_ID_MASK 0x1c00
#define ICP_ICP_QGIC2_GICC_AEOIR_CPU_ID_SHIFT 0xa
#define ICP_ICP_QGIC2_GICC_AEOIR_UNUSED0_MASK 0xffffe000
#define ICP_ICP_QGIC2_GICC_AEOIR_UNUSED0_SHIFT 0xd

#define regICP_ICP_QGIC2_GICC_AHPPIR 0x2028  /*register offset*/
#define ICP_ICP_QGIC2_GICC_AHPPIR_INT_ID_MASK 0x3ff
#define ICP_ICP_QGIC2_GICC_AHPPIR_INT_ID_SHIFT 0x0
#define ICP_ICP_QGIC2_GICC_AHPPIR_CPU_ID_MASK 0x1c00
#define ICP_ICP_QGIC2_GICC_AHPPIR_CPU_ID_SHIFT 0xa
#define ICP_ICP_QGIC2_GICC_AHPPIR_UNUSED0_MASK 0xffffe000
#define ICP_ICP_QGIC2_GICC_AHPPIR_UNUSED0_SHIFT 0xd

#define regICP_ICP_QGIC2_GICC_APR 0x20d0  /*register offset*/
#define ICP_ICP_QGIC2_GICC_APR_PRI_MASK 0xffffffff
#define ICP_ICP_QGIC2_GICC_APR_PRI_SHIFT 0x0

#define regICP_ICP_QGIC2_GICC_NSAPR 0x20e0  /*register offset*/
#define ICP_ICP_QGIC2_GICC_NSAPR_PRI_MASK 0xffffffff
#define ICP_ICP_QGIC2_GICC_NSAPR_PRI_SHIFT 0x0

#define regICP_ICP_QGIC2_GICC_IIDR 0x20fc  /*register offset*/
#define ICP_ICP_QGIC2_GICC_IIDR_IMPLEMENTOR_MASK 0xfff
#define ICP_ICP_QGIC2_GICC_IIDR_IMPLEMENTOR_SHIFT 0x0
#define ICP_ICP_QGIC2_GICC_IIDR_REVISION_MASK 0xf000
#define ICP_ICP_QGIC2_GICC_IIDR_REVISION_SHIFT 0xc
#define ICP_ICP_QGIC2_GICC_IIDR_ARCH_VERSION_MASK 0xf0000
#define ICP_ICP_QGIC2_GICC_IIDR_ARCH_VERSION_SHIFT 0x10
#define ICP_ICP_QGIC2_GICC_IIDR_PART_NUM_MASK 0xfff00000
#define ICP_ICP_QGIC2_GICC_IIDR_PART_NUM_SHIFT 0x14

#define regICP_ICP_QGIC2_GICC_DIR 0x3000  /*register offset*/
#define ICP_ICP_QGIC2_GICC_DIR_INT_ID_MASK 0x3ff
#define ICP_ICP_QGIC2_GICC_DIR_INT_ID_SHIFT 0x0
#define ICP_ICP_QGIC2_GICC_DIR_CPU_ID_MASK 0x1c00
#define ICP_ICP_QGIC2_GICC_DIR_CPU_ID_SHIFT 0xa
#define ICP_ICP_QGIC2_GICC_DIR_UNUSED0_MASK 0xffffe000
#define ICP_ICP_QGIC2_GICC_DIR_UNUSED0_SHIFT 0xd

#define regICP_ICP_QGIC2_GICV_CTLR 0x4000  /*register offset*/
#define ICP_ICP_QGIC2_GICV_CTLR_ENABLE_G0_MASK 0x1
#define ICP_ICP_QGIC2_GICV_CTLR_ENABLE_G0_SHIFT 0x0
#define ICP_ICP_QGIC2_GICV_CTLR_ENABLE_G1_MASK 0x2
#define ICP_ICP_QGIC2_GICV_CTLR_ENABLE_G1_SHIFT 0x1
#define ICP_ICP_QGIC2_GICV_CTLR_ACKCTL_MASK 0x4
#define ICP_ICP_QGIC2_GICV_CTLR_ACKCTL_SHIFT 0x2
#define ICP_ICP_QGIC2_GICV_CTLR_FIQEN_MASK 0x8
#define ICP_ICP_QGIC2_GICV_CTLR_FIQEN_SHIFT 0x3
#define ICP_ICP_QGIC2_GICV_CTLR_GBPR_MASK 0x10
#define ICP_ICP_QGIC2_GICV_CTLR_GBPR_SHIFT 0x4
#define ICP_ICP_QGIC2_GICV_CTLR_UNUSED0_MASK 0x1e0
#define ICP_ICP_QGIC2_GICV_CTLR_UNUSED0_SHIFT 0x5
#define ICP_ICP_QGIC2_GICV_CTLR_EOIMODE_MASK 0x200
#define ICP_ICP_QGIC2_GICV_CTLR_EOIMODE_SHIFT 0x9
#define ICP_ICP_QGIC2_GICV_CTLR_UNUSED1_MASK 0xfffffc00
#define ICP_ICP_QGIC2_GICV_CTLR_UNUSED1_SHIFT 0xa

#define regICP_ICP_QGIC2_GICV_PMR 0x4004  /*register offset*/
#define ICP_ICP_QGIC2_GICV_PMR_UNUSED0_MASK 0x7
#define ICP_ICP_QGIC2_GICV_PMR_UNUSED0_SHIFT 0x0
#define ICP_ICP_QGIC2_GICV_PMR_LEVEL_MASK 0xf8
#define ICP_ICP_QGIC2_GICV_PMR_LEVEL_SHIFT 0x3
#define ICP_ICP_QGIC2_GICV_PMR_UNUSED1_MASK 0xffffff00
#define ICP_ICP_QGIC2_GICV_PMR_UNUSED1_SHIFT 0x8

#define regICP_ICP_QGIC2_GICV_BPR 0x4008  /*register offset*/
#define ICP_ICP_QGIC2_GICV_BPR_VAL_MASK 0x7
#define ICP_ICP_QGIC2_GICV_BPR_VAL_SHIFT 0x0
#define ICP_ICP_QGIC2_GICV_BPR_UNUSED0_MASK 0xfffffff8
#define ICP_ICP_QGIC2_GICV_BPR_UNUSED0_SHIFT 0x3

#define regICP_ICP_QGIC2_GICV_IAR 0x400c  /*register offset*/
#define ICP_ICP_QGIC2_GICV_IAR_INT_ID_MASK 0x3ff
#define ICP_ICP_QGIC2_GICV_IAR_INT_ID_SHIFT 0x0
#define ICP_ICP_QGIC2_GICV_IAR_CPU_ID_MASK 0x1c00
#define ICP_ICP_QGIC2_GICV_IAR_CPU_ID_SHIFT 0xa
#define ICP_ICP_QGIC2_GICV_IAR_UNUSED0_MASK 0xffffe000
#define ICP_ICP_QGIC2_GICV_IAR_UNUSED0_SHIFT 0xd

#define regICP_ICP_QGIC2_GICV_EOIR 0x4010  /*register offset*/
#define ICP_ICP_QGIC2_GICV_EOIR_INT_ID_MASK 0x3ff
#define ICP_ICP_QGIC2_GICV_EOIR_INT_ID_SHIFT 0x0
#define ICP_ICP_QGIC2_GICV_EOIR_CPU_ID_MASK 0x1c00
#define ICP_ICP_QGIC2_GICV_EOIR_CPU_ID_SHIFT 0xa
#define ICP_ICP_QGIC2_GICV_EOIR_UNUSED0_MASK 0xffffe000
#define ICP_ICP_QGIC2_GICV_EOIR_UNUSED0_SHIFT 0xd

#define regICP_ICP_QGIC2_GICV_RPR 0x4014  /*register offset*/
#define ICP_ICP_QGIC2_GICV_RPR_UNUSED0_MASK 0x7
#define ICP_ICP_QGIC2_GICV_RPR_UNUSED0_SHIFT 0x0
#define ICP_ICP_QGIC2_GICV_RPR_VAL_MASK 0xf8
#define ICP_ICP_QGIC2_GICV_RPR_VAL_SHIFT 0x3
#define ICP_ICP_QGIC2_GICV_RPR_UNUSED1_MASK 0xffffff00
#define ICP_ICP_QGIC2_GICV_RPR_UNUSED1_SHIFT 0x8

#define regICP_ICP_QGIC2_GICV_HPPIR 0x4018  /*register offset*/
#define ICP_ICP_QGIC2_GICV_HPPIR_INT_ID_MASK 0x3ff
#define ICP_ICP_QGIC2_GICV_HPPIR_INT_ID_SHIFT 0x0
#define ICP_ICP_QGIC2_GICV_HPPIR_CPU_ID_MASK 0x1c00
#define ICP_ICP_QGIC2_GICV_HPPIR_CPU_ID_SHIFT 0xa
#define ICP_ICP_QGIC2_GICV_HPPIR_UNUSED0_MASK 0xffffe000
#define ICP_ICP_QGIC2_GICV_HPPIR_UNUSED0_SHIFT 0xd

#define regICP_ICP_QGIC2_GICV_ABPR 0x401c  /*register offset*/
#define ICP_ICP_QGIC2_GICV_ABPR_VAL_MASK 0x7
#define ICP_ICP_QGIC2_GICV_ABPR_VAL_SHIFT 0x0
#define ICP_ICP_QGIC2_GICV_ABPR_UNUSED0_MASK 0xfffffff8
#define ICP_ICP_QGIC2_GICV_ABPR_UNUSED0_SHIFT 0x3

#define regICP_ICP_QGIC2_GICV_AIAR 0x4020  /*register offset*/
#define ICP_ICP_QGIC2_GICV_AIAR_INT_ID_MASK 0x3ff
#define ICP_ICP_QGIC2_GICV_AIAR_INT_ID_SHIFT 0x0
#define ICP_ICP_QGIC2_GICV_AIAR_CPU_ID_MASK 0x1c00
#define ICP_ICP_QGIC2_GICV_AIAR_CPU_ID_SHIFT 0xa
#define ICP_ICP_QGIC2_GICV_AIAR_UNUSED0_MASK 0xffffe000
#define ICP_ICP_QGIC2_GICV_AIAR_UNUSED0_SHIFT 0xd

#define regICP_ICP_QGIC2_GICV_AEOIR 0x4024  /*register offset*/
#define ICP_ICP_QGIC2_GICV_AEOIR_INT_ID_MASK 0x3ff
#define ICP_ICP_QGIC2_GICV_AEOIR_INT_ID_SHIFT 0x0
#define ICP_ICP_QGIC2_GICV_AEOIR_CPU_ID_MASK 0x1c00
#define ICP_ICP_QGIC2_GICV_AEOIR_CPU_ID_SHIFT 0xa
#define ICP_ICP_QGIC2_GICV_AEOIR_UNUSED0_MASK 0xffffe000
#define ICP_ICP_QGIC2_GICV_AEOIR_UNUSED0_SHIFT 0xd

#define regICP_ICP_QGIC2_GICV_AHPPIR 0x4028  /*register offset*/
#define ICP_ICP_QGIC2_GICV_AHPPIR_INT_ID_MASK 0x3ff
#define ICP_ICP_QGIC2_GICV_AHPPIR_INT_ID_SHIFT 0x0
#define ICP_ICP_QGIC2_GICV_AHPPIR_CPU_ID_MASK 0x1c00
#define ICP_ICP_QGIC2_GICV_AHPPIR_CPU_ID_SHIFT 0xa
#define ICP_ICP_QGIC2_GICV_AHPPIR_UNUSED0_MASK 0xffffe000
#define ICP_ICP_QGIC2_GICV_AHPPIR_UNUSED0_SHIFT 0xd

#define regICP_ICP_QGIC2_GICV_APR 0x40d0  /*register offset*/
#define ICP_ICP_QGIC2_GICV_APR_PRI_MASK 0xffffffff
#define ICP_ICP_QGIC2_GICV_APR_PRI_SHIFT 0x0

#define regICP_ICP_QGIC2_GICV_IIDR 0x40fc  /*register offset*/
#define ICP_ICP_QGIC2_GICV_IIDR_IMPLEMENTOR_MASK 0xfff
#define ICP_ICP_QGIC2_GICV_IIDR_IMPLEMENTOR_SHIFT 0x0
#define ICP_ICP_QGIC2_GICV_IIDR_REVISION_MASK 0xf000
#define ICP_ICP_QGIC2_GICV_IIDR_REVISION_SHIFT 0xc
#define ICP_ICP_QGIC2_GICV_IIDR_ARCH_VERSION_MASK 0xf0000
#define ICP_ICP_QGIC2_GICV_IIDR_ARCH_VERSION_SHIFT 0x10
#define ICP_ICP_QGIC2_GICV_IIDR_PART_NUM_MASK 0xfff00000
#define ICP_ICP_QGIC2_GICV_IIDR_PART_NUM_SHIFT 0x14

#define regICP_ICP_QGIC2_GICV_DIR 0x5000  /*register offset*/
#define ICP_ICP_QGIC2_GICV_DIR_INT_ID_MASK 0x3ff
#define ICP_ICP_QGIC2_GICV_DIR_INT_ID_SHIFT 0x0
#define ICP_ICP_QGIC2_GICV_DIR_CPU_ID_MASK 0x1c00
#define ICP_ICP_QGIC2_GICV_DIR_CPU_ID_SHIFT 0xa
#define ICP_ICP_QGIC2_GICV_DIR_UNUSED0_MASK 0xffffe000
#define ICP_ICP_QGIC2_GICV_DIR_UNUSED0_SHIFT 0xd

#define regICP_ICP_QTMR_QTMR_AC_CNTFRQ 0x8000  /*register offset*/
#define ICP_ICP_QTMR_QTMR_AC_CNTFRQ_CNTFRQ_MASK 0xffffffff
#define ICP_ICP_QTMR_QTMR_AC_CNTFRQ_CNTFRQ_SHIFT 0x0

#define regICP_ICP_QTMR_QTMR_AC_CNTNSAR_FG0 0x8004  /*register offset*/
#define ICP_ICP_QTMR_QTMR_AC_CNTNSAR_FG0_NSN_MASK 0x3
#define ICP_ICP_QTMR_QTMR_AC_CNTNSAR_FG0_NSN_SHIFT 0x0
#define ICP_ICP_QTMR_QTMR_AC_CNTNSAR_FG0_UNUSED0_MASK 0xfffffffc
#define ICP_ICP_QTMR_QTMR_AC_CNTNSAR_FG0_UNUSED0_SHIFT 0x2

#define regICP_ICP_QTMR_QTMR_AC_CNTTIDR_FG0 0x8008  /*register offset*/
#define ICP_ICP_QTMR_QTMR_AC_CNTTIDR_FG0_F0_CFG_MASK 0xf
#define ICP_ICP_QTMR_QTMR_AC_CNTTIDR_FG0_F0_CFG_SHIFT 0x0
#define ICP_ICP_QTMR_QTMR_AC_CNTTIDR_FG0_F1_CFG_MASK 0xf0
#define ICP_ICP_QTMR_QTMR_AC_CNTTIDR_FG0_F1_CFG_SHIFT 0x4
#define ICP_ICP_QTMR_QTMR_AC_CNTTIDR_FG0_F2_CFG_MASK 0xf00
#define ICP_ICP_QTMR_QTMR_AC_CNTTIDR_FG0_F2_CFG_SHIFT 0x8
#define ICP_ICP_QTMR_QTMR_AC_CNTTIDR_FG0_F3_CFG_MASK 0xf000
#define ICP_ICP_QTMR_QTMR_AC_CNTTIDR_FG0_F3_CFG_SHIFT 0xc
#define ICP_ICP_QTMR_QTMR_AC_CNTTIDR_FG0_F4_CFG_MASK 0xf0000
#define ICP_ICP_QTMR_QTMR_AC_CNTTIDR_FG0_F4_CFG_SHIFT 0x10
#define ICP_ICP_QTMR_QTMR_AC_CNTTIDR_FG0_F5_CFG_MASK 0xf00000
#define ICP_ICP_QTMR_QTMR_AC_CNTTIDR_FG0_F5_CFG_SHIFT 0x14
#define ICP_ICP_QTMR_QTMR_AC_CNTTIDR_FG0_F6_CFG_MASK 0xf000000
#define ICP_ICP_QTMR_QTMR_AC_CNTTIDR_FG0_F6_CFG_SHIFT 0x18
#define ICP_ICP_QTMR_QTMR_AC_CNTTIDR_FG0_F7_CFG_MASK 0xf0000000
#define ICP_ICP_QTMR_QTMR_AC_CNTTIDR_FG0_F7_CFG_SHIFT 0x1c

#define regICP_ICP_QTMR_QTMR_AC_CNTACR0_FG0 0x8040  /*register offset*/
#define ICP_ICP_QTMR_QTMR_AC_CNTACR0_FG0_RPCT_MASK 0x1
#define ICP_ICP_QTMR_QTMR_AC_CNTACR0_FG0_RPCT_SHIFT 0x0
#define ICP_ICP_QTMR_QTMR_AC_CNTACR0_FG0_RPVCT_MASK 0x2
#define ICP_ICP_QTMR_QTMR_AC_CNTACR0_FG0_RPVCT_SHIFT 0x1
#define ICP_ICP_QTMR_QTMR_AC_CNTACR0_FG0_RFRQ_MASK 0x4
#define ICP_ICP_QTMR_QTMR_AC_CNTACR0_FG0_RFRQ_SHIFT 0x2
#define ICP_ICP_QTMR_QTMR_AC_CNTACR0_FG0_RVOFF_MASK 0x8
#define ICP_ICP_QTMR_QTMR_AC_CNTACR0_FG0_RVOFF_SHIFT 0x3
#define ICP_ICP_QTMR_QTMR_AC_CNTACR0_FG0_RWVT_MASK 0x10
#define ICP_ICP_QTMR_QTMR_AC_CNTACR0_FG0_RWVT_SHIFT 0x4
#define ICP_ICP_QTMR_QTMR_AC_CNTACR0_FG0_RWPT_MASK 0x20
#define ICP_ICP_QTMR_QTMR_AC_CNTACR0_FG0_RWPT_SHIFT 0x5
#define ICP_ICP_QTMR_QTMR_AC_CNTACR0_FG0_UNUSED0_MASK 0xffffffc0
#define ICP_ICP_QTMR_QTMR_AC_CNTACR0_FG0_UNUSED0_SHIFT 0x6

#define regICP_ICP_QTMR_QTMR_AC_CNTACR1_FG0 0x8044  /*register offset*/
#define ICP_ICP_QTMR_QTMR_AC_CNTACR1_FG0_RPCT_MASK 0x1
#define ICP_ICP_QTMR_QTMR_AC_CNTACR1_FG0_RPCT_SHIFT 0x0
#define ICP_ICP_QTMR_QTMR_AC_CNTACR1_FG0_RPVCT_MASK 0x2
#define ICP_ICP_QTMR_QTMR_AC_CNTACR1_FG0_RPVCT_SHIFT 0x1
#define ICP_ICP_QTMR_QTMR_AC_CNTACR1_FG0_RFRQ_MASK 0x4
#define ICP_ICP_QTMR_QTMR_AC_CNTACR1_FG0_RFRQ_SHIFT 0x2
#define ICP_ICP_QTMR_QTMR_AC_CNTACR1_FG0_RVOFF_MASK 0x8
#define ICP_ICP_QTMR_QTMR_AC_CNTACR1_FG0_RVOFF_SHIFT 0x3
#define ICP_ICP_QTMR_QTMR_AC_CNTACR1_FG0_RWVT_MASK 0x10
#define ICP_ICP_QTMR_QTMR_AC_CNTACR1_FG0_RWVT_SHIFT 0x4
#define ICP_ICP_QTMR_QTMR_AC_CNTACR1_FG0_RWPT_MASK 0x20
#define ICP_ICP_QTMR_QTMR_AC_CNTACR1_FG0_RWPT_SHIFT 0x5
#define ICP_ICP_QTMR_QTMR_AC_CNTACR1_FG0_UNUSED0_MASK 0xffffffc0
#define ICP_ICP_QTMR_QTMR_AC_CNTACR1_FG0_UNUSED0_SHIFT 0x6

#define regICP_ICP_QTMR_QTMR_AC_CNTVOFF_FG0_LO_0 0x8080  /*register offset*/
#define ICP_ICP_QTMR_QTMR_AC_CNTVOFF_FG0_LO_0_CNTVOFF_LO_MASK 0xffffffff
#define ICP_ICP_QTMR_QTMR_AC_CNTVOFF_FG0_LO_0_CNTVOFF_LO_SHIFT 0x0

#define regICP_ICP_QTMR_QTMR_AC_CNTVOFF_FG0_HI_0 0x8084  /*register offset*/
#define ICP_ICP_QTMR_QTMR_AC_CNTVOFF_FG0_HI_0_CNTVOFF_HI_MASK 0xffffff
#define ICP_ICP_QTMR_QTMR_AC_CNTVOFF_FG0_HI_0_CNTVOFF_HI_SHIFT 0x0
#define ICP_ICP_QTMR_QTMR_AC_CNTVOFF_FG0_HI_0_UNUSED0_MASK 0xff000000
#define ICP_ICP_QTMR_QTMR_AC_CNTVOFF_FG0_HI_0_UNUSED0_SHIFT 0x18

#define regICP_ICP_QTMR_QTMR_AC_CNTVOFF_FG0_LO_1 0x8088  /*register offset*/
#define ICP_ICP_QTMR_QTMR_AC_CNTVOFF_FG0_LO_1_CNTVOFF_LO_MASK 0xffffffff
#define ICP_ICP_QTMR_QTMR_AC_CNTVOFF_FG0_LO_1_CNTVOFF_LO_SHIFT 0x0

#define regICP_ICP_QTMR_QTMR_AC_CNTVOFF_FG0_HI_1 0x808c  /*register offset*/
#define ICP_ICP_QTMR_QTMR_AC_CNTVOFF_FG0_HI_1_CNTVOFF_HI_MASK 0xffffff
#define ICP_ICP_QTMR_QTMR_AC_CNTVOFF_FG0_HI_1_CNTVOFF_HI_SHIFT 0x0
#define ICP_ICP_QTMR_QTMR_AC_CNTVOFF_FG0_HI_1_UNUSED0_MASK 0xff000000
#define ICP_ICP_QTMR_QTMR_AC_CNTVOFF_FG0_HI_1_UNUSED0_SHIFT 0x18

#define regICP_ICP_QTMR_QTMR_AC_CFG 0x8fc0  /*register offset*/
#define ICP_ICP_QTMR_QTMR_AC_CFG_TEST_BUS_EN_MASK 0x1
#define ICP_ICP_QTMR_QTMR_AC_CFG_TEST_BUS_EN_SHIFT 0x0
#define ICP_ICP_QTMR_QTMR_AC_CFG_DSBL_ATOMIC_MASK 0x2
#define ICP_ICP_QTMR_QTMR_AC_CFG_DSBL_ATOMIC_SHIFT 0x1
#define ICP_ICP_QTMR_QTMR_AC_CFG_UNUSED0_MASK 0xfffffffc
#define ICP_ICP_QTMR_QTMR_AC_CFG_UNUSED0_SHIFT 0x2

#define regICP_ICP_QTMR_QTMR_AC_VERSION 0x8fd0  /*register offset*/
#define ICP_ICP_QTMR_QTMR_AC_VERSION_STEP_MASK 0xffff
#define ICP_ICP_QTMR_QTMR_AC_VERSION_STEP_SHIFT 0x0
#define ICP_ICP_QTMR_QTMR_AC_VERSION_MINOR_MASK 0xfff0000
#define ICP_ICP_QTMR_QTMR_AC_VERSION_MINOR_SHIFT 0x10
#define ICP_ICP_QTMR_QTMR_AC_VERSION_MAJOR_MASK 0xf0000000
#define ICP_ICP_QTMR_QTMR_AC_VERSION_MAJOR_SHIFT 0x1c

#define regICP_ICP_QTMR_QTMR_AC_HW_FRAME_SEL_1 0x8fe0  /*register offset*/
#define ICP_ICP_QTMR_QTMR_AC_HW_FRAME_SEL_1_HW_FRAME_SEL1_MASK 0xffffffff
#define ICP_ICP_QTMR_QTMR_AC_HW_FRAME_SEL_1_HW_FRAME_SEL1_SHIFT 0x0

#define regICP_ICP_QTMR_QTMR_AC_HW_FRAME_SEL_2 0x8ff0  /*register offset*/
#define ICP_ICP_QTMR_QTMR_AC_HW_FRAME_SEL_2_HW_FRAME_SEL2_MASK 0xffffffff
#define ICP_ICP_QTMR_QTMR_AC_HW_FRAME_SEL_2_HW_FRAME_SEL2_SHIFT 0x0

#define regICP_ICP_QTMR_QTMR_V1_CNTPCT_LO 0x9000  /*register offset*/
#define ICP_ICP_QTMR_QTMR_V1_CNTPCT_LO_CNTPCT_LO_MASK 0xffffffff
#define ICP_ICP_QTMR_QTMR_V1_CNTPCT_LO_CNTPCT_LO_SHIFT 0x0

#define regICP_ICP_QTMR_QTMR_V1_CNTPCT_HI 0x9004  /*register offset*/
#define ICP_ICP_QTMR_QTMR_V1_CNTPCT_HI_CNTPCT_HI_MASK 0xffffff
#define ICP_ICP_QTMR_QTMR_V1_CNTPCT_HI_CNTPCT_HI_SHIFT 0x0
#define ICP_ICP_QTMR_QTMR_V1_CNTPCT_HI_UNUSED0_MASK 0xff000000
#define ICP_ICP_QTMR_QTMR_V1_CNTPCT_HI_UNUSED0_SHIFT 0x18

#define regICP_ICP_QTMR_QTMR_V1_CNTVCT_LO 0x9008  /*register offset*/
#define ICP_ICP_QTMR_QTMR_V1_CNTVCT_LO_CNTVCT_LO_MASK 0xffffffff
#define ICP_ICP_QTMR_QTMR_V1_CNTVCT_LO_CNTVCT_LO_SHIFT 0x0

#define regICP_ICP_QTMR_QTMR_V1_CNTVCT_HI 0x900c  /*register offset*/
#define ICP_ICP_QTMR_QTMR_V1_CNTVCT_HI_CNTVCT_HI_MASK 0xffffff
#define ICP_ICP_QTMR_QTMR_V1_CNTVCT_HI_CNTVCT_HI_SHIFT 0x0
#define ICP_ICP_QTMR_QTMR_V1_CNTVCT_HI_UNUSED0_MASK 0xff000000
#define ICP_ICP_QTMR_QTMR_V1_CNTVCT_HI_UNUSED0_SHIFT 0x18

#define regICP_ICP_QTMR_QTMR_V1_CNTFRQ 0x9010  /*register offset*/
#define ICP_ICP_QTMR_QTMR_V1_CNTFRQ_CNTFRQ_MASK 0xffffffff
#define ICP_ICP_QTMR_QTMR_V1_CNTFRQ_CNTFRQ_SHIFT 0x0

#define regICP_ICP_QTMR_QTMR_V1_CNTPL0ACR 0x9014  /*register offset*/
#define ICP_ICP_QTMR_QTMR_V1_CNTPL0ACR_PL0PCTEN_MASK 0x1
#define ICP_ICP_QTMR_QTMR_V1_CNTPL0ACR_PL0PCTEN_SHIFT 0x0
#define ICP_ICP_QTMR_QTMR_V1_CNTPL0ACR_PL0VCTEN_MASK 0x2
#define ICP_ICP_QTMR_QTMR_V1_CNTPL0ACR_PL0VCTEN_SHIFT 0x1
#define ICP_ICP_QTMR_QTMR_V1_CNTPL0ACR_UNUSED0_MASK 0xfc
#define ICP_ICP_QTMR_QTMR_V1_CNTPL0ACR_UNUSED0_SHIFT 0x2
#define ICP_ICP_QTMR_QTMR_V1_CNTPL0ACR_PL0VTEN_MASK 0x100
#define ICP_ICP_QTMR_QTMR_V1_CNTPL0ACR_PL0VTEN_SHIFT 0x8
#define ICP_ICP_QTMR_QTMR_V1_CNTPL0ACR_PL0CTEN_MASK 0x200
#define ICP_ICP_QTMR_QTMR_V1_CNTPL0ACR_PL0CTEN_SHIFT 0x9
#define ICP_ICP_QTMR_QTMR_V1_CNTPL0ACR_UNUSED1_MASK 0xfffffc00
#define ICP_ICP_QTMR_QTMR_V1_CNTPL0ACR_UNUSED1_SHIFT 0xa

#define regICP_ICP_QTMR_QTMR_V1_CNTVOFF_LO 0x9018  /*register offset*/
#define ICP_ICP_QTMR_QTMR_V1_CNTVOFF_LO_CNTVOFF_L0_MASK 0xffffffff
#define ICP_ICP_QTMR_QTMR_V1_CNTVOFF_LO_CNTVOFF_L0_SHIFT 0x0

#define regICP_ICP_QTMR_QTMR_V1_CNTVOFF_HI 0x901c  /*register offset*/
#define ICP_ICP_QTMR_QTMR_V1_CNTVOFF_HI_CNTVOFF_HI_MASK 0xffffff
#define ICP_ICP_QTMR_QTMR_V1_CNTVOFF_HI_CNTVOFF_HI_SHIFT 0x0
#define ICP_ICP_QTMR_QTMR_V1_CNTVOFF_HI_UNUSED0_MASK 0xff000000
#define ICP_ICP_QTMR_QTMR_V1_CNTVOFF_HI_UNUSED0_SHIFT 0x18

#define regICP_ICP_QTMR_QTMR_V1_CNTP_CVAL_LO 0x9020  /*register offset*/
#define ICP_ICP_QTMR_QTMR_V1_CNTP_CVAL_LO_CNTP_CVAL_L0_MASK 0xffffffff
#define ICP_ICP_QTMR_QTMR_V1_CNTP_CVAL_LO_CNTP_CVAL_L0_SHIFT 0x0

#define regICP_ICP_QTMR_QTMR_V1_CNTP_CVAL_HI 0x9024  /*register offset*/
#define ICP_ICP_QTMR_QTMR_V1_CNTP_CVAL_HI_CNTP_CVAL_HI_MASK 0xffffff
#define ICP_ICP_QTMR_QTMR_V1_CNTP_CVAL_HI_CNTP_CVAL_HI_SHIFT 0x0
#define ICP_ICP_QTMR_QTMR_V1_CNTP_CVAL_HI_UNUSED0_MASK 0xff000000
#define ICP_ICP_QTMR_QTMR_V1_CNTP_CVAL_HI_UNUSED0_SHIFT 0x18

#define regICP_ICP_QTMR_QTMR_V1_CNTP_TVAL 0x9028  /*register offset*/
#define ICP_ICP_QTMR_QTMR_V1_CNTP_TVAL_CNTP_TVAL_MASK 0xffffffff
#define ICP_ICP_QTMR_QTMR_V1_CNTP_TVAL_CNTP_TVAL_SHIFT 0x0

#define regICP_ICP_QTMR_QTMR_V1_CNTP_CTL 0x902c  /*register offset*/
#define ICP_ICP_QTMR_QTMR_V1_CNTP_CTL_EN_MASK 0x1
#define ICP_ICP_QTMR_QTMR_V1_CNTP_CTL_EN_SHIFT 0x0
#define ICP_ICP_QTMR_QTMR_V1_CNTP_CTL_IMSK_MASK 0x2
#define ICP_ICP_QTMR_QTMR_V1_CNTP_CTL_IMSK_SHIFT 0x1
#define ICP_ICP_QTMR_QTMR_V1_CNTP_CTL_ISTAT_MASK 0x4
#define ICP_ICP_QTMR_QTMR_V1_CNTP_CTL_ISTAT_SHIFT 0x2
#define ICP_ICP_QTMR_QTMR_V1_CNTP_CTL_UNUSED0_MASK 0xfffffff8
#define ICP_ICP_QTMR_QTMR_V1_CNTP_CTL_UNUSED0_SHIFT 0x3

#define regICP_ICP_QTMR_QTMR_V1_CNTV_CVAL_LO 0x9030  /*register offset*/
#define ICP_ICP_QTMR_QTMR_V1_CNTV_CVAL_LO_CNTV_CVAL_L0_MASK 0xffffffff
#define ICP_ICP_QTMR_QTMR_V1_CNTV_CVAL_LO_CNTV_CVAL_L0_SHIFT 0x0

#define regICP_ICP_QTMR_QTMR_V1_CNTV_CVAL_HI 0x9034  /*register offset*/
#define ICP_ICP_QTMR_QTMR_V1_CNTV_CVAL_HI_CNTV_CVAL_HI_MASK 0xffffff
#define ICP_ICP_QTMR_QTMR_V1_CNTV_CVAL_HI_CNTV_CVAL_HI_SHIFT 0x0
#define ICP_ICP_QTMR_QTMR_V1_CNTV_CVAL_HI_UNUSED0_MASK 0xff000000
#define ICP_ICP_QTMR_QTMR_V1_CNTV_CVAL_HI_UNUSED0_SHIFT 0x18

#define regICP_ICP_QTMR_QTMR_V1_CNTV_TVAL 0x9038  /*register offset*/
#define ICP_ICP_QTMR_QTMR_V1_CNTV_TVAL_CNTV_TVAL_MASK 0xffffffff
#define ICP_ICP_QTMR_QTMR_V1_CNTV_TVAL_CNTV_TVAL_SHIFT 0x0

#define regICP_ICP_QTMR_QTMR_V1_CNTV_CTL 0x903c  /*register offset*/
#define ICP_ICP_QTMR_QTMR_V1_CNTV_CTL_EN_MASK 0x1
#define ICP_ICP_QTMR_QTMR_V1_CNTV_CTL_EN_SHIFT 0x0
#define ICP_ICP_QTMR_QTMR_V1_CNTV_CTL_IMSK_MASK 0x2
#define ICP_ICP_QTMR_QTMR_V1_CNTV_CTL_IMSK_SHIFT 0x1
#define ICP_ICP_QTMR_QTMR_V1_CNTV_CTL_ISTAT_MASK 0x4
#define ICP_ICP_QTMR_QTMR_V1_CNTV_CTL_ISTAT_SHIFT 0x2
#define ICP_ICP_QTMR_QTMR_V1_CNTV_CTL_UNUSED0_MASK 0xfffffff8
#define ICP_ICP_QTMR_QTMR_V1_CNTV_CTL_UNUSED0_SHIFT 0x3

#define regICP_ICP_QTMR_QTMR_V1_VERSION 0x9fd0  /*register offset*/
#define ICP_ICP_QTMR_QTMR_V1_VERSION_STEP_MASK 0xffff
#define ICP_ICP_QTMR_QTMR_V1_VERSION_STEP_SHIFT 0x0
#define ICP_ICP_QTMR_QTMR_V1_VERSION_MINOR_MASK 0xfff0000
#define ICP_ICP_QTMR_QTMR_V1_VERSION_MINOR_SHIFT 0x10
#define ICP_ICP_QTMR_QTMR_V1_VERSION_MAJOR_MASK 0xf0000000
#define ICP_ICP_QTMR_QTMR_V1_VERSION_MAJOR_SHIFT 0x1c

#define regICP_ICP_QTMR_QTMR_V2_CNTPCT_LO 0xa000  /*register offset*/
#define ICP_ICP_QTMR_QTMR_V2_CNTPCT_LO_CNTPCT_LO_MASK 0xffffffff
#define ICP_ICP_QTMR_QTMR_V2_CNTPCT_LO_CNTPCT_LO_SHIFT 0x0

#define regICP_ICP_QTMR_QTMR_V2_CNTPCT_HI 0xa004  /*register offset*/
#define ICP_ICP_QTMR_QTMR_V2_CNTPCT_HI_CNTPCT_HI_MASK 0xffffff
#define ICP_ICP_QTMR_QTMR_V2_CNTPCT_HI_CNTPCT_HI_SHIFT 0x0
#define ICP_ICP_QTMR_QTMR_V2_CNTPCT_HI_UNUSED0_MASK 0xff000000
#define ICP_ICP_QTMR_QTMR_V2_CNTPCT_HI_UNUSED0_SHIFT 0x18

#define regICP_ICP_QTMR_QTMR_V2_CNTVCT_LO 0xa008  /*register offset*/
#define ICP_ICP_QTMR_QTMR_V2_CNTVCT_LO_CNTVCT_LO_MASK 0xffffffff
#define ICP_ICP_QTMR_QTMR_V2_CNTVCT_LO_CNTVCT_LO_SHIFT 0x0

#define regICP_ICP_QTMR_QTMR_V2_CNTVCT_HI 0xa00c  /*register offset*/
#define ICP_ICP_QTMR_QTMR_V2_CNTVCT_HI_CNTVCT_HI_MASK 0xffffff
#define ICP_ICP_QTMR_QTMR_V2_CNTVCT_HI_CNTVCT_HI_SHIFT 0x0
#define ICP_ICP_QTMR_QTMR_V2_CNTVCT_HI_UNUSED0_MASK 0xff000000
#define ICP_ICP_QTMR_QTMR_V2_CNTVCT_HI_UNUSED0_SHIFT 0x18

#define regICP_ICP_QTMR_QTMR_V2_CNTFRQ 0xa010  /*register offset*/
#define ICP_ICP_QTMR_QTMR_V2_CNTFRQ_CNTFRQ_MASK 0xffffffff
#define ICP_ICP_QTMR_QTMR_V2_CNTFRQ_CNTFRQ_SHIFT 0x0

#define regICP_ICP_QTMR_QTMR_V2_CNTP_CVAL_LO 0xa020  /*register offset*/
#define ICP_ICP_QTMR_QTMR_V2_CNTP_CVAL_LO_CNTP_CVAL_L0_MASK 0xffffffff
#define ICP_ICP_QTMR_QTMR_V2_CNTP_CVAL_LO_CNTP_CVAL_L0_SHIFT 0x0

#define regICP_ICP_QTMR_QTMR_V2_CNTP_CVAL_HI 0xa024  /*register offset*/
#define ICP_ICP_QTMR_QTMR_V2_CNTP_CVAL_HI_CNTP_CVAL_HI_MASK 0xffffff
#define ICP_ICP_QTMR_QTMR_V2_CNTP_CVAL_HI_CNTP_CVAL_HI_SHIFT 0x0
#define ICP_ICP_QTMR_QTMR_V2_CNTP_CVAL_HI_UNUSED0_MASK 0xff000000
#define ICP_ICP_QTMR_QTMR_V2_CNTP_CVAL_HI_UNUSED0_SHIFT 0x18

#define regICP_ICP_QTMR_QTMR_V2_CNTP_TVAL 0xa028  /*register offset*/
#define ICP_ICP_QTMR_QTMR_V2_CNTP_TVAL_CNTP_TVAL_MASK 0xffffffff
#define ICP_ICP_QTMR_QTMR_V2_CNTP_TVAL_CNTP_TVAL_SHIFT 0x0

#define regICP_ICP_QTMR_QTMR_V2_CNTP_CTL 0xa02c  /*register offset*/
#define ICP_ICP_QTMR_QTMR_V2_CNTP_CTL_EN_MASK 0x1
#define ICP_ICP_QTMR_QTMR_V2_CNTP_CTL_EN_SHIFT 0x0
#define ICP_ICP_QTMR_QTMR_V2_CNTP_CTL_IMSK_MASK 0x2
#define ICP_ICP_QTMR_QTMR_V2_CNTP_CTL_IMSK_SHIFT 0x1
#define ICP_ICP_QTMR_QTMR_V2_CNTP_CTL_ISTAT_MASK 0x4
#define ICP_ICP_QTMR_QTMR_V2_CNTP_CTL_ISTAT_SHIFT 0x2
#define ICP_ICP_QTMR_QTMR_V2_CNTP_CTL_UNUSED0_MASK 0xfffffff8
#define ICP_ICP_QTMR_QTMR_V2_CNTP_CTL_UNUSED0_SHIFT 0x3

#define regICP_ICP_QTMR_QTMR_V2_CNTV_CVAL_LO 0xa030  /*register offset*/
#define ICP_ICP_QTMR_QTMR_V2_CNTV_CVAL_LO_CNTV_CVAL_L0_MASK 0xffffffff
#define ICP_ICP_QTMR_QTMR_V2_CNTV_CVAL_LO_CNTV_CVAL_L0_SHIFT 0x0

#define regICP_ICP_QTMR_QTMR_V2_CNTV_CVAL_HI 0xa034  /*register offset*/
#define ICP_ICP_QTMR_QTMR_V2_CNTV_CVAL_HI_CNTV_CVAL_HI_MASK 0xffffff
#define ICP_ICP_QTMR_QTMR_V2_CNTV_CVAL_HI_CNTV_CVAL_HI_SHIFT 0x0
#define ICP_ICP_QTMR_QTMR_V2_CNTV_CVAL_HI_UNUSED0_MASK 0xff000000
#define ICP_ICP_QTMR_QTMR_V2_CNTV_CVAL_HI_UNUSED0_SHIFT 0x18

#define regICP_ICP_QTMR_QTMR_V2_CNTV_TVAL 0xa038  /*register offset*/
#define ICP_ICP_QTMR_QTMR_V2_CNTV_TVAL_CNTV_TVAL_MASK 0xffffffff
#define ICP_ICP_QTMR_QTMR_V2_CNTV_TVAL_CNTV_TVAL_SHIFT 0x0

#define regICP_ICP_QTMR_QTMR_V2_CNTV_CTL 0xa03c  /*register offset*/
#define ICP_ICP_QTMR_QTMR_V2_CNTV_CTL_EN_MASK 0x1
#define ICP_ICP_QTMR_QTMR_V2_CNTV_CTL_EN_SHIFT 0x0
#define ICP_ICP_QTMR_QTMR_V2_CNTV_CTL_IMSK_MASK 0x2
#define ICP_ICP_QTMR_QTMR_V2_CNTV_CTL_IMSK_SHIFT 0x1
#define ICP_ICP_QTMR_QTMR_V2_CNTV_CTL_ISTAT_MASK 0x4
#define ICP_ICP_QTMR_QTMR_V2_CNTV_CTL_ISTAT_SHIFT 0x2
#define ICP_ICP_QTMR_QTMR_V2_CNTV_CTL_UNUSED0_MASK 0xfffffff8
#define ICP_ICP_QTMR_QTMR_V2_CNTV_CTL_UNUSED0_SHIFT 0x3

#define regICP_ICP_QTMR_QTMR_V2_VERSION 0xafd0  /*register offset*/
#define ICP_ICP_QTMR_QTMR_V2_VERSION_STEP_MASK 0xffff
#define ICP_ICP_QTMR_QTMR_V2_VERSION_STEP_SHIFT 0x0
#define ICP_ICP_QTMR_QTMR_V2_VERSION_MINOR_MASK 0xfff0000
#define ICP_ICP_QTMR_QTMR_V2_VERSION_MINOR_SHIFT 0x10
#define ICP_ICP_QTMR_QTMR_V2_VERSION_MAJOR_MASK 0xf0000000
#define ICP_ICP_QTMR_QTMR_V2_VERSION_MAJOR_SHIFT 0x1c

#define regICP_ICP_QTMR_QTMR_WDT_CSR 0xb000  /*register offset*/
#define ICP_ICP_QTMR_QTMR_WDT_CSR_WDT_EN_MASK 0x1
#define ICP_ICP_QTMR_QTMR_WDT_CSR_WDT_EN_SHIFT 0x0
#define ICP_ICP_QTMR_QTMR_WDT_CSR_WS0_MASK 0x2
#define ICP_ICP_QTMR_QTMR_WDT_CSR_WS0_SHIFT 0x1
#define ICP_ICP_QTMR_QTMR_WDT_CSR_WS1_MASK 0x4
#define ICP_ICP_QTMR_QTMR_WDT_CSR_WS1_SHIFT 0x2
#define ICP_ICP_QTMR_QTMR_WDT_CSR_WDT_FREEZE_EN_MASK 0x8
#define ICP_ICP_QTMR_QTMR_WDT_CSR_WDT_FREEZE_EN_SHIFT 0x3
#define ICP_ICP_QTMR_QTMR_WDT_CSR_UNUSED0_MASK 0xfffffff0
#define ICP_ICP_QTMR_QTMR_WDT_CSR_UNUSED0_SHIFT 0x4

#define regICP_ICP_QTMR_QTMR_WDT_OFFSET 0xb008  /*register offset*/
#define ICP_ICP_QTMR_QTMR_WDT_OFFSET_WDT_OFFSET_MASK 0xffffffff
#define ICP_ICP_QTMR_QTMR_WDT_OFFSET_WDT_OFFSET_SHIFT 0x0

#define regICP_ICP_QTMR_QTMR_WDT_CVAL_LO 0xb010  /*register offset*/
#define ICP_ICP_QTMR_QTMR_WDT_CVAL_LO_CVAL_LO_MASK 0xffffffff
#define ICP_ICP_QTMR_QTMR_WDT_CVAL_LO_CVAL_LO_SHIFT 0x0

#define regICP_ICP_QTMR_QTMR_WDT_CVAL_HI 0xb014  /*register offset*/
#define ICP_ICP_QTMR_QTMR_WDT_CVAL_HI_CVAL_HI_MASK 0xffffff
#define ICP_ICP_QTMR_QTMR_WDT_CVAL_HI_CVAL_HI_SHIFT 0x0
#define ICP_ICP_QTMR_QTMR_WDT_CVAL_HI_UNUSED0_MASK 0xff000000
#define ICP_ICP_QTMR_QTMR_WDT_CVAL_HI_UNUSED0_SHIFT 0x18

#define regICP_ICP_QTMR_QTMR_WDT_CTL_IIDR 0xbfcc  /*register offset*/
#define ICP_ICP_QTMR_QTMR_WDT_CTL_IIDR_JEP_ID_CODE_MASK 0x7f
#define ICP_ICP_QTMR_QTMR_WDT_CTL_IIDR_JEP_ID_CODE_SHIFT 0x0
#define ICP_ICP_QTMR_QTMR_WDT_CTL_IIDR_UNUSED0_MASK 0x80
#define ICP_ICP_QTMR_QTMR_WDT_CTL_IIDR_UNUSED0_SHIFT 0x7
#define ICP_ICP_QTMR_QTMR_WDT_CTL_IIDR_JEP_CONT_CODE_MASK 0xf00
#define ICP_ICP_QTMR_QTMR_WDT_CTL_IIDR_JEP_CONT_CODE_SHIFT 0x8
#define ICP_ICP_QTMR_QTMR_WDT_CTL_IIDR_IMPL_REV_MASK 0xf000
#define ICP_ICP_QTMR_QTMR_WDT_CTL_IIDR_IMPL_REV_SHIFT 0xc
#define ICP_ICP_QTMR_QTMR_WDT_CTL_IIDR_ARCH_VERSION_MASK 0xf0000
#define ICP_ICP_QTMR_QTMR_WDT_CTL_IIDR_ARCH_VERSION_SHIFT 0x10
#define ICP_ICP_QTMR_QTMR_WDT_CTL_IIDR_PDT_ID_MASK 0xfff00000
#define ICP_ICP_QTMR_QTMR_WDT_CTL_IIDR_PDT_ID_SHIFT 0x14

#define regICP_ICP_QTMR_QTMR_WDT_CTL_VERSION 0xbfd0  /*register offset*/
#define ICP_ICP_QTMR_QTMR_WDT_CTL_VERSION_STEP_MASK 0xffff
#define ICP_ICP_QTMR_QTMR_WDT_CTL_VERSION_STEP_SHIFT 0x0
#define ICP_ICP_QTMR_QTMR_WDT_CTL_VERSION_MINOR_MASK 0xfff0000
#define ICP_ICP_QTMR_QTMR_WDT_CTL_VERSION_MINOR_SHIFT 0x10
#define ICP_ICP_QTMR_QTMR_WDT_CTL_VERSION_MAJOR_MASK 0xf0000000
#define ICP_ICP_QTMR_QTMR_WDT_CTL_VERSION_MAJOR_SHIFT 0x1c

#define regICP_ICP_QTMR_QTMR_WDT_CTL_PIDR2 0xbfe8  /*register offset*/
#define ICP_ICP_QTMR_QTMR_WDT_CTL_PIDR2_PIDR_FLD1_MASK 0xf
#define ICP_ICP_QTMR_QTMR_WDT_CTL_PIDR2_PIDR_FLD1_SHIFT 0x0
#define ICP_ICP_QTMR_QTMR_WDT_CTL_PIDR2_ARCH_REV_MASK 0xf0
#define ICP_ICP_QTMR_QTMR_WDT_CTL_PIDR2_ARCH_REV_SHIFT 0x4
#define ICP_ICP_QTMR_QTMR_WDT_CTL_PIDR2_PIDR_FLD2_MASK 0xffffff00
#define ICP_ICP_QTMR_QTMR_WDT_CTL_PIDR2_PIDR_FLD2_SHIFT 0x8

#define regICP_ICP_QTMR_QTMR_WDT_RR 0xc000  /*register offset*/
#define ICP_ICP_QTMR_QTMR_WDT_RR_WRR_MASK 0xffffffff
#define ICP_ICP_QTMR_QTMR_WDT_RR_WRR_SHIFT 0x0

#define regICP_ICP_QTMR_QTMR_WDT_REF_IIDR 0xcfcc  /*register offset*/
#define ICP_ICP_QTMR_QTMR_WDT_REF_IIDR_JEP_ID_CODE_MASK 0x7f
#define ICP_ICP_QTMR_QTMR_WDT_REF_IIDR_JEP_ID_CODE_SHIFT 0x0
#define ICP_ICP_QTMR_QTMR_WDT_REF_IIDR_UNUSED0_MASK 0x80
#define ICP_ICP_QTMR_QTMR_WDT_REF_IIDR_UNUSED0_SHIFT 0x7
#define ICP_ICP_QTMR_QTMR_WDT_REF_IIDR_JEP_CONT_CODE_MASK 0xf00
#define ICP_ICP_QTMR_QTMR_WDT_REF_IIDR_JEP_CONT_CODE_SHIFT 0x8
#define ICP_ICP_QTMR_QTMR_WDT_REF_IIDR_IMPL_REV_MASK 0xf000
#define ICP_ICP_QTMR_QTMR_WDT_REF_IIDR_IMPL_REV_SHIFT 0xc
#define ICP_ICP_QTMR_QTMR_WDT_REF_IIDR_ARCH_VERSION_MASK 0xf0000
#define ICP_ICP_QTMR_QTMR_WDT_REF_IIDR_ARCH_VERSION_SHIFT 0x10
#define ICP_ICP_QTMR_QTMR_WDT_REF_IIDR_PDT_ID_MASK 0xfff00000
#define ICP_ICP_QTMR_QTMR_WDT_REF_IIDR_PDT_ID_SHIFT 0x14

#define regICP_ICP_QTMR_QTMR_WDT_REF_VERSION 0xcfd0  /*register offset*/
#define ICP_ICP_QTMR_QTMR_WDT_REF_VERSION_STEP_MASK 0xffff
#define ICP_ICP_QTMR_QTMR_WDT_REF_VERSION_STEP_SHIFT 0x0
#define ICP_ICP_QTMR_QTMR_WDT_REF_VERSION_MINOR_MASK 0xfff0000
#define ICP_ICP_QTMR_QTMR_WDT_REF_VERSION_MINOR_SHIFT 0x10
#define ICP_ICP_QTMR_QTMR_WDT_REF_VERSION_MAJOR_MASK 0xf0000000
#define ICP_ICP_QTMR_QTMR_WDT_REF_VERSION_MAJOR_SHIFT 0x1c

#define regICP_ICP_QTMR_QTMR_WDT_REF_PIDR2 0xcfe8  /*register offset*/
#define ICP_ICP_QTMR_QTMR_WDT_REF_PIDR2_PIDR_FLD1_MASK 0xf
#define ICP_ICP_QTMR_QTMR_WDT_REF_PIDR2_PIDR_FLD1_SHIFT 0x0
#define ICP_ICP_QTMR_QTMR_WDT_REF_PIDR2_ARCH_VERSION_MASK 0xf0
#define ICP_ICP_QTMR_QTMR_WDT_REF_PIDR2_ARCH_VERSION_SHIFT 0x4
#define ICP_ICP_QTMR_QTMR_WDT_REF_PIDR2_PIDR_FLD2_MASK 0xffffff00
#define ICP_ICP_QTMR_QTMR_WDT_REF_PIDR2_PIDR_FLD2_SHIFT 0x8

#define regICP_ICP_SIERRA_A5_HW_VERSION 0x10000  /*register offset*/
#define ICP_ICP_SIERRA_A5_HW_VERSION_STEP_MASK 0xffff
#define ICP_ICP_SIERRA_A5_HW_VERSION_STEP_SHIFT 0x0
#define ICP_ICP_SIERRA_A5_HW_VERSION_MINOR_MASK 0xfff0000
#define ICP_ICP_SIERRA_A5_HW_VERSION_MINOR_SHIFT 0x10
#define ICP_ICP_SIERRA_A5_HW_VERSION_MAJOR_MASK 0xf0000000
#define ICP_ICP_SIERRA_A5_HW_VERSION_MAJOR_SHIFT 0x1c

#define regICP_ICP_SIERRA_A5_CSR_NSEC_RESET 0x10004  /*register offset*/
#define ICP_ICP_SIERRA_A5_CSR_NSEC_RESET_CSR_TIMER_RESET_MASK 0x1
#define ICP_ICP_SIERRA_A5_CSR_NSEC_RESET_CSR_TIMER_RESET_SHIFT 0x0
#define ICP_ICP_SIERRA_A5_CSR_NSEC_RESET_CSR_QGIC_RESET_MASK 0x2
#define ICP_ICP_SIERRA_A5_CSR_NSEC_RESET_CSR_QGIC_RESET_SHIFT 0x1
#define ICP_ICP_SIERRA_A5_CSR_NSEC_RESET_CSR_CPU_RESET_MASK 0x4
#define ICP_ICP_SIERRA_A5_CSR_NSEC_RESET_CSR_CPU_RESET_SHIFT 0x2
#define ICP_ICP_SIERRA_A5_CSR_NSEC_RESET_CSR_DBG_RESET_MASK 0x8
#define ICP_ICP_SIERRA_A5_CSR_NSEC_RESET_CSR_DBG_RESET_SHIFT 0x3
#define ICP_ICP_SIERRA_A5_CSR_NSEC_RESET_CSR_FUNC_RESET_MASK 0x10
#define ICP_ICP_SIERRA_A5_CSR_NSEC_RESET_CSR_FUNC_RESET_SHIFT 0x4
#define ICP_ICP_SIERRA_A5_CSR_NSEC_RESET_UNUSED0_MASK 0xffffffe0
#define ICP_ICP_SIERRA_A5_CSR_NSEC_RESET_UNUSED0_SHIFT 0x5

#define regICP_ICP_SIERRA_A5_CSR_A5_CONTROL 0x10008  /*register offset*/
#define ICP_ICP_SIERRA_A5_CSR_A5_CONTROL_CSR_VINITHI_MASK 0x1
#define ICP_ICP_SIERRA_A5_CSR_A5_CONTROL_CSR_VINITHI_SHIFT 0x0
#define ICP_ICP_SIERRA_A5_CSR_A5_CONTROL_CSR_TEINIT_MASK 0x2
#define ICP_ICP_SIERRA_A5_CSR_A5_CONTROL_CSR_TEINIT_SHIFT 0x1
#define ICP_ICP_SIERRA_A5_CSR_A5_CONTROL_UNUSED0_MASK 0x4
#define ICP_ICP_SIERRA_A5_CSR_A5_CONTROL_UNUSED0_SHIFT 0x2
#define ICP_ICP_SIERRA_A5_CSR_A5_CONTROL_CSR_L1RSTDISABLE_MASK 0x8
#define ICP_ICP_SIERRA_A5_CSR_A5_CONTROL_CSR_L1RSTDISABLE_SHIFT 0x3
#define ICP_ICP_SIERRA_A5_CSR_A5_CONTROL_CSR_WAKE_UP_EN_MASK 0x10
#define ICP_ICP_SIERRA_A5_CSR_A5_CONTROL_CSR_WAKE_UP_EN_SHIFT 0x4
#define ICP_ICP_SIERRA_A5_CSR_A5_CONTROL_CSR_CFGEND_MASK 0x20
#define ICP_ICP_SIERRA_A5_CSR_A5_CONTROL_CSR_CFGEND_SHIFT 0x5
#define ICP_ICP_SIERRA_A5_CSR_A5_CONTROL_CSR_CP15SDISABLE_MASK 0x40
#define ICP_ICP_SIERRA_A5_CSR_A5_CONTROL_CSR_CP15SDISABLE_SHIFT 0x6
#define ICP_ICP_SIERRA_A5_CSR_A5_CONTROL_UNUSED1_MASK 0x180
#define ICP_ICP_SIERRA_A5_CSR_A5_CONTROL_UNUSED1_SHIFT 0x7
#define ICP_ICP_SIERRA_A5_CSR_A5_CONTROL_CSR_A5_CPU_EN_MASK 0x200
#define ICP_ICP_SIERRA_A5_CSR_A5_CONTROL_CSR_A5_CPU_EN_SHIFT 0x9
#define ICP_ICP_SIERRA_A5_CSR_A5_CONTROL_CSR_WDT_FREEZE_MASK 0x400
#define ICP_ICP_SIERRA_A5_CSR_A5_CONTROL_CSR_WDT_FREEZE_SHIFT 0xa
#define ICP_ICP_SIERRA_A5_CSR_A5_CONTROL_CSR_GEN_EVENT_MASK 0x800
#define ICP_ICP_SIERRA_A5_CSR_A5_CONTROL_CSR_GEN_EVENT_SHIFT 0xb
#define ICP_ICP_SIERRA_A5_CSR_A5_CONTROL_CSR_EN_CLKGATE_WFI_MASK 0x1000
#define ICP_ICP_SIERRA_A5_CSR_A5_CONTROL_CSR_EN_CLKGATE_WFI_SHIFT 0xc
#define ICP_ICP_SIERRA_A5_CSR_A5_CONTROL_CSR_EN_CLKGATE_WFE_MASK 0x2000
#define ICP_ICP_SIERRA_A5_CSR_A5_CONTROL_CSR_EN_CLKGATE_WFE_SHIFT 0xd
#define ICP_ICP_SIERRA_A5_CSR_A5_CONTROL_CSR_EDBGRQ_MASK 0x4000
#define ICP_ICP_SIERRA_A5_CSR_A5_CONTROL_CSR_EDBGRQ_SHIFT 0xe
#define ICP_ICP_SIERRA_A5_CSR_A5_CONTROL_UNUSED2_MASK 0x78000
#define ICP_ICP_SIERRA_A5_CSR_A5_CONTROL_UNUSED2_SHIFT 0xf
#define ICP_ICP_SIERRA_A5_CSR_A5_CONTROL_CSR_TSMAXWIDTH_MASK 0x80000
#define ICP_ICP_SIERRA_A5_CSR_A5_CONTROL_CSR_TSMAXWIDTH_SHIFT 0x13
#define ICP_ICP_SIERRA_A5_CSR_A5_CONTROL_CSR_TSNATURAL_MASK 0x100000
#define ICP_ICP_SIERRA_A5_CSR_A5_CONTROL_CSR_TSNATURAL_SHIFT 0x14
#define ICP_ICP_SIERRA_A5_CSR_A5_CONTROL_UNUSED3_MASK 0x200000
#define ICP_ICP_SIERRA_A5_CSR_A5_CONTROL_UNUSED3_SHIFT 0x15
#define ICP_ICP_SIERRA_A5_CSR_A5_CONTROL_CSR_DBGSWENABLE_MASK 0x400000
#define ICP_ICP_SIERRA_A5_CSR_A5_CONTROL_CSR_DBGSWENABLE_SHIFT 0x16
#define ICP_ICP_SIERRA_A5_CSR_A5_CONTROL_UNUSED4_MASK 0xff800000
#define ICP_ICP_SIERRA_A5_CSR_A5_CONTROL_UNUSED4_SHIFT 0x17

#define regICP_ICP_SIERRA_A5_CSR_ETM 0x1000c  /*register offset*/
#define ICP_ICP_SIERRA_A5_CSR_ETM_CSR_ETM_MAXEXTIN_MASK 0x7
#define ICP_ICP_SIERRA_A5_CSR_ETM_CSR_ETM_MAXEXTIN_SHIFT 0x0
#define ICP_ICP_SIERRA_A5_CSR_ETM_UNUSED0_MASK 0x8
#define ICP_ICP_SIERRA_A5_CSR_ETM_UNUSED0_SHIFT 0x3
#define ICP_ICP_SIERRA_A5_CSR_ETM_CSR_ETM_MAXEXTOUT_MASK 0x30
#define ICP_ICP_SIERRA_A5_CSR_ETM_CSR_ETM_MAXEXTOUT_SHIFT 0x4
#define ICP_ICP_SIERRA_A5_CSR_ETM_UNUSED1_MASK 0xc0
#define ICP_ICP_SIERRA_A5_CSR_ETM_UNUSED1_SHIFT 0x6
#define ICP_ICP_SIERRA_A5_CSR_ETM_CSR_ETM_MAXCORES_MASK 0x700
#define ICP_ICP_SIERRA_A5_CSR_ETM_CSR_ETM_MAXCORES_SHIFT 0x8
#define ICP_ICP_SIERRA_A5_CSR_ETM_UNUSED2_MASK 0xf800
#define ICP_ICP_SIERRA_A5_CSR_ETM_UNUSED2_SHIFT 0xb
#define ICP_ICP_SIERRA_A5_CSR_ETM_CSR_ETMEN_MASK 0x10000
#define ICP_ICP_SIERRA_A5_CSR_ETM_CSR_ETMEN_SHIFT 0x10
#define ICP_ICP_SIERRA_A5_CSR_ETM_CSR_ETMSTANDBYWFX_MASK 0x20000
#define ICP_ICP_SIERRA_A5_CSR_ETM_CSR_ETMSTANDBYWFX_SHIFT 0x11
#define ICP_ICP_SIERRA_A5_CSR_ETM_UNUSED3_MASK 0xfffc0000
#define ICP_ICP_SIERRA_A5_CSR_ETM_UNUSED3_SHIFT 0x12

#define regICP_ICP_SIERRA_A5_CSR_A2HOSTINTEN 0x10010  /*register offset*/
#define ICP_ICP_SIERRA_A5_CSR_A2HOSTINTEN_A2HOSTINTEN_MASK 0x1
#define ICP_ICP_SIERRA_A5_CSR_A2HOSTINTEN_A2HOSTINTEN_SHIFT 0x0
#define ICP_ICP_SIERRA_A5_CSR_A2HOSTINTEN_WDT_WS0EN_MASK 0x2
#define ICP_ICP_SIERRA_A5_CSR_A2HOSTINTEN_WDT_WS0EN_SHIFT 0x1
#define ICP_ICP_SIERRA_A5_CSR_A2HOSTINTEN_WDT_WS1EN_MASK 0x4
#define ICP_ICP_SIERRA_A5_CSR_A2HOSTINTEN_WDT_WS1EN_SHIFT 0x2
#define ICP_ICP_SIERRA_A5_CSR_A2HOSTINTEN_UNUSED0_MASK 0xfffffff8
#define ICP_ICP_SIERRA_A5_CSR_A2HOSTINTEN_UNUSED0_SHIFT 0x3

#define regICP_ICP_SIERRA_A5_CSR_A2HOSTINT 0x10014  /*register offset*/
#define ICP_ICP_SIERRA_A5_CSR_A2HOSTINT_A2HOSTINT_MASK 0x1
#define ICP_ICP_SIERRA_A5_CSR_A2HOSTINT_A2HOSTINT_SHIFT 0x0
#define ICP_ICP_SIERRA_A5_CSR_A2HOSTINT_UNUSED0_MASK 0xfffffffe
#define ICP_ICP_SIERRA_A5_CSR_A2HOSTINT_UNUSED0_SHIFT 0x1

#define regICP_ICP_SIERRA_A5_CSR_A2HOSTINTCLR 0x10018  /*register offset*/
#define ICP_ICP_SIERRA_A5_CSR_A2HOSTINTCLR_A2HOSTINTCLR_MASK 0x1
#define ICP_ICP_SIERRA_A5_CSR_A2HOSTINTCLR_A2HOSTINTCLR_SHIFT 0x0
#define ICP_ICP_SIERRA_A5_CSR_A2HOSTINTCLR_WDT_WS0ENCLR_MASK 0x2
#define ICP_ICP_SIERRA_A5_CSR_A2HOSTINTCLR_WDT_WS0ENCLR_SHIFT 0x1
#define ICP_ICP_SIERRA_A5_CSR_A2HOSTINTCLR_WDT_WS1ENCLR_MASK 0x4
#define ICP_ICP_SIERRA_A5_CSR_A2HOSTINTCLR_WDT_WS1ENCLR_SHIFT 0x2
#define ICP_ICP_SIERRA_A5_CSR_A2HOSTINTCLR_UNUSED0_MASK 0xfffffff8
#define ICP_ICP_SIERRA_A5_CSR_A2HOSTINTCLR_UNUSED0_SHIFT 0x3

#define regICP_ICP_SIERRA_A5_CSR_A2HOSTINTSTATUS 0x1001c  /*register offset*/
#define ICP_ICP_SIERRA_A5_CSR_A2HOSTINTSTATUS_A2HOSTINT_MASK 0x1
#define ICP_ICP_SIERRA_A5_CSR_A2HOSTINTSTATUS_A2HOSTINT_SHIFT 0x0
#define ICP_ICP_SIERRA_A5_CSR_A2HOSTINTSTATUS_WDT_WS0_MASK 0x2
#define ICP_ICP_SIERRA_A5_CSR_A2HOSTINTSTATUS_WDT_WS0_SHIFT 0x1
#define ICP_ICP_SIERRA_A5_CSR_A2HOSTINTSTATUS_WDT_WS1_MASK 0x4
#define ICP_ICP_SIERRA_A5_CSR_A2HOSTINTSTATUS_WDT_WS1_SHIFT 0x2
#define ICP_ICP_SIERRA_A5_CSR_A2HOSTINTSTATUS_UNUSED0_MASK 0xfffffff8
#define ICP_ICP_SIERRA_A5_CSR_A2HOSTINTSTATUS_UNUSED0_SHIFT 0x3

#define regICP_ICP_SIERRA_A5_CSR_A2HOSTINTSET 0x10020  /*register offset*/
#define ICP_ICP_SIERRA_A5_CSR_A2HOSTINTSET_A2HOSTINT_MASK 0x1
#define ICP_ICP_SIERRA_A5_CSR_A2HOSTINTSET_A2HOSTINT_SHIFT 0x0
#define ICP_ICP_SIERRA_A5_CSR_A2HOSTINTSET_WDT_WS0_MASK 0x2
#define ICP_ICP_SIERRA_A5_CSR_A2HOSTINTSET_WDT_WS0_SHIFT 0x1
#define ICP_ICP_SIERRA_A5_CSR_A2HOSTINTSET_WDT_WS1_MASK 0x4
#define ICP_ICP_SIERRA_A5_CSR_A2HOSTINTSET_WDT_WS1_SHIFT 0x2
#define ICP_ICP_SIERRA_A5_CSR_A2HOSTINTSET_UNUSED0_MASK 0xfffffff8
#define ICP_ICP_SIERRA_A5_CSR_A2HOSTINTSET_UNUSED0_SHIFT 0x3

#define regICP_ICP_SIERRA_A5_CSR_HOST2ICPINT 0x10030  /*register offset*/
#define ICP_ICP_SIERRA_A5_CSR_HOST2ICPINT_HOSTINT_MASK 0x1
#define ICP_ICP_SIERRA_A5_CSR_HOST2ICPINT_HOSTINT_SHIFT 0x0
#define ICP_ICP_SIERRA_A5_CSR_HOST2ICPINT_UNUSED0_MASK 0xfffffffe
#define ICP_ICP_SIERRA_A5_CSR_HOST2ICPINT_UNUSED0_SHIFT 0x1

#define regICP_ICP_SIERRA_A5_CSR_SYS_CACHE_CTRL 0x10034  /*register offset*/
#define ICP_ICP_SIERRA_A5_CSR_SYS_CACHE_CTRL_SYS_CACHE_MODE_MASK 0x3
#define ICP_ICP_SIERRA_A5_CSR_SYS_CACHE_CTRL_SYS_CACHE_MODE_SHIFT 0x0
#define ICP_ICP_SIERRA_A5_CSR_SYS_CACHE_CTRL_UNUSED0_MASK 0xc
#define ICP_ICP_SIERRA_A5_CSR_SYS_CACHE_CTRL_UNUSED0_SHIFT 0x2
#define ICP_ICP_SIERRA_A5_CSR_SYS_CACHE_CTRL_SYS_CACHE_AR_OVERRIDE_EN_MASK 0x10
#define ICP_ICP_SIERRA_A5_CSR_SYS_CACHE_CTRL_SYS_CACHE_AR_OVERRIDE_EN_SHIFT 0x4
#define ICP_ICP_SIERRA_A5_CSR_SYS_CACHE_CTRL_SYS_CACHE_AW_OVERRIDE_EN_MASK 0x20
#define ICP_ICP_SIERRA_A5_CSR_SYS_CACHE_CTRL_SYS_CACHE_AW_OVERRIDE_EN_SHIFT 0x5
#define ICP_ICP_SIERRA_A5_CSR_SYS_CACHE_CTRL_UNUSED1_MASK 0xc0
#define ICP_ICP_SIERRA_A5_CSR_SYS_CACHE_CTRL_UNUSED1_SHIFT 0x6
#define ICP_ICP_SIERRA_A5_CSR_SYS_CACHE_CTRL_SYS_CACHE_INDEX_MASK 0x1f00
#define ICP_ICP_SIERRA_A5_CSR_SYS_CACHE_CTRL_SYS_CACHE_INDEX_SHIFT 0x8
#define ICP_ICP_SIERRA_A5_CSR_SYS_CACHE_CTRL_SYS_CACHE_AR_MIN_FOOTPRINT_MASK 0x2000
#define ICP_ICP_SIERRA_A5_CSR_SYS_CACHE_CTRL_SYS_CACHE_AR_MIN_FOOTPRINT_SHIFT 0xd
#define ICP_ICP_SIERRA_A5_CSR_SYS_CACHE_CTRL_SYS_CACHE_AW_MIN_FOOTPRINT_MASK 0x4000
#define ICP_ICP_SIERRA_A5_CSR_SYS_CACHE_CTRL_SYS_CACHE_AW_MIN_FOOTPRINT_SHIFT 0xe
#define ICP_ICP_SIERRA_A5_CSR_SYS_CACHE_CTRL_UNUSED2_MASK 0x8000
#define ICP_ICP_SIERRA_A5_CSR_SYS_CACHE_CTRL_UNUSED2_SHIFT 0xf
#define ICP_ICP_SIERRA_A5_CSR_SYS_CACHE_CTRL_SYS_CACHE_AW_CACHE_VALUE_MASK 0xf0000
#define ICP_ICP_SIERRA_A5_CSR_SYS_CACHE_CTRL_SYS_CACHE_AW_CACHE_VALUE_SHIFT 0x10
#define ICP_ICP_SIERRA_A5_CSR_SYS_CACHE_CTRL_SYS_CACHE_AR_CACHE_VALUE_MASK 0xf00000
#define ICP_ICP_SIERRA_A5_CSR_SYS_CACHE_CTRL_SYS_CACHE_AR_CACHE_VALUE_SHIFT 0x14
#define ICP_ICP_SIERRA_A5_CSR_SYS_CACHE_CTRL_UNUSED3_MASK 0xff000000
#define ICP_ICP_SIERRA_A5_CSR_SYS_CACHE_CTRL_UNUSED3_SHIFT 0x18

#define regICP_ICP_SIERRA_A5_CSR_ACESS 0x1003c  /*register offset*/
#define ICP_ICP_SIERRA_A5_CSR_ACESS_AR_QOS_MASK 0xf
#define ICP_ICP_SIERRA_A5_CSR_ACESS_AR_QOS_SHIFT 0x0
#define ICP_ICP_SIERRA_A5_CSR_ACESS_UNUSED0_MASK 0xf0
#define ICP_ICP_SIERRA_A5_CSR_ACESS_UNUSED0_SHIFT 0x4
#define ICP_ICP_SIERRA_A5_CSR_ACESS_AW_QOS_MASK 0xf00
#define ICP_ICP_SIERRA_A5_CSR_ACESS_AW_QOS_SHIFT 0x8
#define ICP_ICP_SIERRA_A5_CSR_ACESS_UNUSED1_MASK 0xfffff000
#define ICP_ICP_SIERRA_A5_CSR_ACESS_UNUSED1_SHIFT 0xc

#define regICP_ICP_SIERRA_A5_CSR_CA5_GP_0_REG 0x10040  /*register offset*/
#define ICP_ICP_SIERRA_A5_CSR_CA5_GP_0_REG_GP_REG_MASK 0xffffffff
#define ICP_ICP_SIERRA_A5_CSR_CA5_GP_0_REG_GP_REG_SHIFT 0x0

#define regICP_ICP_SIERRA_A5_CSR_CA5_GP_1_REG 0x10044  /*register offset*/
#define ICP_ICP_SIERRA_A5_CSR_CA5_GP_1_REG_GP_REG_MASK 0xffffffff
#define ICP_ICP_SIERRA_A5_CSR_CA5_GP_1_REG_GP_REG_SHIFT 0x0

#define regICP_ICP_SIERRA_A5_CSR_CA5_GP_2_REG 0x10048  /*register offset*/
#define ICP_ICP_SIERRA_A5_CSR_CA5_GP_2_REG_GP_REG_MASK 0xffffffff
#define ICP_ICP_SIERRA_A5_CSR_CA5_GP_2_REG_GP_REG_SHIFT 0x0

#define regICP_ICP_SIERRA_A5_CSR_CA5_GP_3_REG 0x1004c  /*register offset*/
#define ICP_ICP_SIERRA_A5_CSR_CA5_GP_3_REG_GP_REG_MASK 0xffffffff
#define ICP_ICP_SIERRA_A5_CSR_CA5_GP_3_REG_GP_REG_SHIFT 0x0

#define regICP_ICP_SIERRA_A5_CSR_CA5_GP_4_REG 0x10050  /*register offset*/
#define ICP_ICP_SIERRA_A5_CSR_CA5_GP_4_REG_GP_REG_MASK 0xffffffff
#define ICP_ICP_SIERRA_A5_CSR_CA5_GP_4_REG_GP_REG_SHIFT 0x0

#define regICP_ICP_SIERRA_A5_CSR_CA5_GP_5_REG 0x10054  /*register offset*/
#define ICP_ICP_SIERRA_A5_CSR_CA5_GP_5_REG_GP_REG_MASK 0xffffffff
#define ICP_ICP_SIERRA_A5_CSR_CA5_GP_5_REG_GP_REG_SHIFT 0x0

#define regICP_ICP_SIERRA_A5_CSR_CA5_GP_6_REG 0x10058  /*register offset*/
#define ICP_ICP_SIERRA_A5_CSR_CA5_GP_6_REG_GP_REG_MASK 0xffffffff
#define ICP_ICP_SIERRA_A5_CSR_CA5_GP_6_REG_GP_REG_SHIFT 0x0

#define regICP_ICP_SIERRA_A5_CSR_CA5_GP_7_REG 0x1005c  /*register offset*/
#define ICP_ICP_SIERRA_A5_CSR_CA5_GP_7_REG_GP_REG_MASK 0xffffffff
#define ICP_ICP_SIERRA_A5_CSR_CA5_GP_7_REG_GP_REG_SHIFT 0x0

#define regICP_ICP_SIERRA_A5_CSR_CA5_GP_8_REG 0x10060  /*register offset*/
#define ICP_ICP_SIERRA_A5_CSR_CA5_GP_8_REG_GP_REG_MASK 0xffffffff
#define ICP_ICP_SIERRA_A5_CSR_CA5_GP_8_REG_GP_REG_SHIFT 0x0

#define regICP_ICP_SIERRA_A5_CSR_CA5_GP_9_REG 0x10064  /*register offset*/
#define ICP_ICP_SIERRA_A5_CSR_CA5_GP_9_REG_GP_REG_MASK 0xffffffff
#define ICP_ICP_SIERRA_A5_CSR_CA5_GP_9_REG_GP_REG_SHIFT 0x0

#define regICP_ICP_SIERRA_A5_CSR_CA5_GP_10_REG 0x10068  /*register offset*/
#define ICP_ICP_SIERRA_A5_CSR_CA5_GP_10_REG_GP_REG_MASK 0xffffffff
#define ICP_ICP_SIERRA_A5_CSR_CA5_GP_10_REG_GP_REG_SHIFT 0x0

#define regICP_ICP_SIERRA_A5_CSR_CA5_GP_11_REG 0x1006c  /*register offset*/
#define ICP_ICP_SIERRA_A5_CSR_CA5_GP_11_REG_GP_REG_MASK 0xffffffff
#define ICP_ICP_SIERRA_A5_CSR_CA5_GP_11_REG_GP_REG_SHIFT 0x0

#define regICP_ICP_SIERRA_A5_CSR_CA5_GP_12_REG 0x10070  /*register offset*/
#define ICP_ICP_SIERRA_A5_CSR_CA5_GP_12_REG_GP_REG_MASK 0xffffffff
#define ICP_ICP_SIERRA_A5_CSR_CA5_GP_12_REG_GP_REG_SHIFT 0x0

#define regICP_ICP_SIERRA_A5_CSR_CA5_GP_13_REG 0x10074  /*register offset*/
#define ICP_ICP_SIERRA_A5_CSR_CA5_GP_13_REG_GP_REG_MASK 0xffffffff
#define ICP_ICP_SIERRA_A5_CSR_CA5_GP_13_REG_GP_REG_SHIFT 0x0

#define regICP_ICP_SIERRA_A5_CSR_CA5_GP_14_REG 0x10078  /*register offset*/
#define ICP_ICP_SIERRA_A5_CSR_CA5_GP_14_REG_GP_REG_MASK 0xffffffff
#define ICP_ICP_SIERRA_A5_CSR_CA5_GP_14_REG_GP_REG_SHIFT 0x0

#define regICP_ICP_SIERRA_A5_CSR_CA5_GP_15_REG 0x1007c  /*register offset*/
#define ICP_ICP_SIERRA_A5_CSR_CA5_GP_15_REG_GP_REG_MASK 0xffffffff
#define ICP_ICP_SIERRA_A5_CSR_CA5_GP_15_REG_GP_REG_SHIFT 0x0

#define regICP_ICP_SIERRA_A5_CSR_CA5_GP_16_REG 0x10080  /*register offset*/
#define ICP_ICP_SIERRA_A5_CSR_CA5_GP_16_REG_GP_REG_MASK 0xffffffff
#define ICP_ICP_SIERRA_A5_CSR_CA5_GP_16_REG_GP_REG_SHIFT 0x0

#define regICP_ICP_SIERRA_A5_CSR_CA5_GP_17_REG 0x10084  /*register offset*/
#define ICP_ICP_SIERRA_A5_CSR_CA5_GP_17_REG_GP_REG_MASK 0xffffffff
#define ICP_ICP_SIERRA_A5_CSR_CA5_GP_17_REG_GP_REG_SHIFT 0x0

#define regICP_ICP_SIERRA_A5_CSR_CA5_GP_18_REG 0x10088  /*register offset*/
#define ICP_ICP_SIERRA_A5_CSR_CA5_GP_18_REG_GP_REG_MASK 0xffffffff
#define ICP_ICP_SIERRA_A5_CSR_CA5_GP_18_REG_GP_REG_SHIFT 0x0

#define regICP_ICP_SIERRA_A5_CSR_CA5_GP_19_REG 0x1008c  /*register offset*/
#define ICP_ICP_SIERRA_A5_CSR_CA5_GP_19_REG_GP_REG_MASK 0xffffffff
#define ICP_ICP_SIERRA_A5_CSR_CA5_GP_19_REG_GP_REG_SHIFT 0x0

#define regICP_ICP_SIERRA_A5_CSR_A5_STATUS 0x10200  /*register offset*/
#define ICP_ICP_SIERRA_A5_CSR_A5_STATUS_UNUSED0_MASK 0x7f
#define ICP_ICP_SIERRA_A5_CSR_A5_STATUS_UNUSED0_SHIFT 0x0
#define ICP_ICP_SIERRA_A5_CSR_A5_STATUS_CSR_A5_STANDBYWFI_MASK 0x80
#define ICP_ICP_SIERRA_A5_CSR_A5_STATUS_CSR_A5_STANDBYWFI_SHIFT 0x7
#define ICP_ICP_SIERRA_A5_CSR_A5_STATUS_CSR_A5_STANDBYWFE_MASK 0x100
#define ICP_ICP_SIERRA_A5_CSR_A5_STATUS_CSR_A5_STANDBYWFE_SHIFT 0x8
#define ICP_ICP_SIERRA_A5_CSR_A5_STATUS_CSR_A5_CLK_STATUS_MASK 0x200
#define ICP_ICP_SIERRA_A5_CSR_A5_STATUS_CSR_A5_CLK_STATUS_SHIFT 0x9
#define ICP_ICP_SIERRA_A5_CSR_A5_STATUS_UNUSED1_MASK 0xfffffc00
#define ICP_ICP_SIERRA_A5_CSR_A5_STATUS_UNUSED1_SHIFT 0xa

#define regICP_ICP_SIERRA_A5_QGIC2_LM_ID 0x10204  /*register offset*/
#define ICP_ICP_SIERRA_A5_QGIC2_LM_ID_CFG_LM_MID_MASK 0x7f
#define ICP_ICP_SIERRA_A5_QGIC2_LM_ID_CFG_LM_MID_SHIFT 0x0
#define ICP_ICP_SIERRA_A5_QGIC2_LM_ID_UNUSED0_MASK 0x80
#define ICP_ICP_SIERRA_A5_QGIC2_LM_ID_UNUSED0_SHIFT 0x7
#define ICP_ICP_SIERRA_A5_QGIC2_LM_ID_CFG_LM_PID_MASK 0xf00
#define ICP_ICP_SIERRA_A5_QGIC2_LM_ID_CFG_LM_PID_SHIFT 0x8
#define ICP_ICP_SIERRA_A5_QGIC2_LM_ID_UNUSED1_MASK 0xf000
#define ICP_ICP_SIERRA_A5_QGIC2_LM_ID_UNUSED1_SHIFT 0xc
#define ICP_ICP_SIERRA_A5_QGIC2_LM_ID_CFG_LM_BID_MASK 0x70000
#define ICP_ICP_SIERRA_A5_QGIC2_LM_ID_CFG_LM_BID_SHIFT 0x10
#define ICP_ICP_SIERRA_A5_QGIC2_LM_ID_UNUSED2_MASK 0xfff80000
#define ICP_ICP_SIERRA_A5_QGIC2_LM_ID_UNUSED2_SHIFT 0x13

#define regICP_ICP_SIERRA_A5_SPARE 0x10400  /*register offset*/
#define ICP_ICP_SIERRA_A5_SPARE_SPARE_MASK 0x1
#define ICP_ICP_SIERRA_A5_SPARE_SPARE_SHIFT 0x0
#define ICP_ICP_SIERRA_A5_SPARE_UNUSED0_MASK 0xfffffffe
#define ICP_ICP_SIERRA_A5_SPARE_UNUSED0_SHIFT 0x1

#define regICP_ICP_CSR_TITAN_VERSION 0x18000  /*register offset*/
#define ICP_ICP_CSR_TITAN_VERSION_STEP_MASK 0xff
#define ICP_ICP_CSR_TITAN_VERSION_STEP_SHIFT 0x0
#define ICP_ICP_CSR_TITAN_VERSION_TIER_MASK 0xff00
#define ICP_ICP_CSR_TITAN_VERSION_TIER_SHIFT 0x8
#define ICP_ICP_CSR_TITAN_VERSION_GENERATION_MASK 0xff0000
#define ICP_ICP_CSR_TITAN_VERSION_GENERATION_SHIFT 0x10
#define ICP_ICP_CSR_TITAN_VERSION_UNUSED0_MASK 0xff000000
#define ICP_ICP_CSR_TITAN_VERSION_UNUSED0_SHIFT 0x18

#define regICP_ICP_CSR_HW_VERSION 0x18004  /*register offset*/
#define ICP_ICP_CSR_HW_VERSION_STEP_MASK 0xffff
#define ICP_ICP_CSR_HW_VERSION_STEP_SHIFT 0x0
#define ICP_ICP_CSR_HW_VERSION_MINOR_MASK 0xfff0000
#define ICP_ICP_CSR_HW_VERSION_MINOR_SHIFT 0x10
#define ICP_ICP_CSR_HW_VERSION_MAJOR_MASK 0xf0000000
#define ICP_ICP_CSR_HW_VERSION_MAJOR_SHIFT 0x1c

#define regICP_ICP_CSR_SPARE 0x18200  /*register offset*/
#define ICP_ICP_CSR_SPARE_SPARE_MASK 0x1
#define ICP_ICP_CSR_SPARE_SPARE_SHIFT 0x0
#define ICP_ICP_CSR_SPARE_UNUSED0_MASK 0xfffffffe
#define ICP_ICP_CSR_SPARE_UNUSED0_SHIFT 0x1

/*----------------------------------------------------------------------
        Register Data Structures
----------------------------------------------------------------------*/

typedef struct{
    unsigned  ENABLE : 1; /* 0:0 */
    unsigned  ENABLE_NS : 1; /* 1:1 */
    unsigned  UNUSED0 : 30; /* 31:2 */
} _icp_icp_qgic2_gicd_ctlr;

typedef union{
    _icp_icp_qgic2_gicd_ctlr bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QGIC2_GICD_CTLR;

typedef struct{
    unsigned  IT_LINES : 5; /* 4:0 */
    unsigned  CPU_NUM : 3; /* 7:5 */
    unsigned  UNUSED0 : 2; /* 9:8 */
    unsigned  TZ : 1; /* 10:10 */
    unsigned  LSPI : 5; /* 15:11 */
    unsigned  UNUSED1 : 16; /* 31:16 */
} _icp_icp_qgic2_gicd_typer;

typedef union{
    _icp_icp_qgic2_gicd_typer bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QGIC2_GICD_TYPER;

typedef struct{
    unsigned  IMPLEMENTOR : 12; /* 11:0 */
    unsigned  REVISION : 4; /* 15:12 */
    unsigned  UNUSED0 : 16; /* 31:16 */
} _icp_icp_qgic2_gicd_iidr;

typedef union{
    _icp_icp_qgic2_gicd_iidr bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QGIC2_GICD_IIDR;

typedef struct{
    unsigned  GICD_CGCR : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _icp_icp_qgic2_gicd_ansacr;

typedef union{
    _icp_icp_qgic2_gicd_ansacr bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QGIC2_GICD_ANSACR;

typedef struct{
    unsigned  DI_RD : 1; /* 0:0 */
    unsigned  DI_DEMET : 1; /* 1:1 */
    unsigned  DI_PPI_SPI_STATE : 1; /* 2:2 */
    unsigned  DI_SGI_STATE : 1; /* 3:3 */
    unsigned  UNUSED0 : 12; /* 15:4 */
    unsigned  TOP : 1; /* 16:16 */
    unsigned  UNUSED1 : 15; /* 31:17 */
} _icp_icp_qgic2_gicd_cgcr;

typedef union{
    _icp_icp_qgic2_gicd_cgcr bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QGIC2_GICD_CGCR;

typedef struct{
    unsigned  STEP : 16; /* 15:0 */
    unsigned  MINOR : 12; /* 27:16 */
    unsigned  MAJOR : 4; /* 31:28 */
} _icp_icp_qgic2_gicd_hw_version;

typedef union{
    _icp_icp_qgic2_gicd_hw_version bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QGIC2_GICD_HW_VERSION;

typedef struct{
    unsigned  INT_NS : 32; /* 31:0 */
} _icp_icp_qgic2_gicd_isr0;

typedef union{
    _icp_icp_qgic2_gicd_isr0 bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QGIC2_GICD_ISR0;

typedef struct{
    unsigned  INT_NS : 32; /* 31:0 */
} _icp_icp_qgic2_gicd_isr1;

typedef union{
    _icp_icp_qgic2_gicd_isr1 bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QGIC2_GICD_ISR1;

typedef struct{
    unsigned  INT_NS : 32; /* 31:0 */
} _icp_icp_qgic2_gicd_isr2;

typedef union{
    _icp_icp_qgic2_gicd_isr2 bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QGIC2_GICD_ISR2;

typedef struct{
    unsigned  INT : 32; /* 31:0 */
} _icp_icp_qgic2_gicd_isenabler0;

typedef union{
    _icp_icp_qgic2_gicd_isenabler0 bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QGIC2_GICD_ISENABLER0;

typedef struct{
    unsigned  INT : 32; /* 31:0 */
} _icp_icp_qgic2_gicd_isenabler1;

typedef union{
    _icp_icp_qgic2_gicd_isenabler1 bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QGIC2_GICD_ISENABLER1;

typedef struct{
    unsigned  INT : 32; /* 31:0 */
} _icp_icp_qgic2_gicd_isenabler2;

typedef union{
    _icp_icp_qgic2_gicd_isenabler2 bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QGIC2_GICD_ISENABLER2;

typedef struct{
    unsigned  INT : 32; /* 31:0 */
} _icp_icp_qgic2_gicd_icenabler0;

typedef union{
    _icp_icp_qgic2_gicd_icenabler0 bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QGIC2_GICD_ICENABLER0;

typedef struct{
    unsigned  INT : 32; /* 31:0 */
} _icp_icp_qgic2_gicd_icenabler1;

typedef union{
    _icp_icp_qgic2_gicd_icenabler1 bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QGIC2_GICD_ICENABLER1;

typedef struct{
    unsigned  INT : 32; /* 31:0 */
} _icp_icp_qgic2_gicd_icenabler2;

typedef union{
    _icp_icp_qgic2_gicd_icenabler2 bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QGIC2_GICD_ICENABLER2;

typedef struct{
    unsigned  INT : 32; /* 31:0 */
} _icp_icp_qgic2_gicd_ispendr0;

typedef union{
    _icp_icp_qgic2_gicd_ispendr0 bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QGIC2_GICD_ISPENDR0;

typedef struct{
    unsigned  INT : 32; /* 31:0 */
} _icp_icp_qgic2_gicd_ispendr1;

typedef union{
    _icp_icp_qgic2_gicd_ispendr1 bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QGIC2_GICD_ISPENDR1;

typedef struct{
    unsigned  INT : 32; /* 31:0 */
} _icp_icp_qgic2_gicd_ispendr2;

typedef union{
    _icp_icp_qgic2_gicd_ispendr2 bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QGIC2_GICD_ISPENDR2;

typedef struct{
    unsigned  INT : 32; /* 31:0 */
} _icp_icp_qgic2_gicd_icpendr0;

typedef union{
    _icp_icp_qgic2_gicd_icpendr0 bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QGIC2_GICD_ICPENDR0;

typedef struct{
    unsigned  INT : 32; /* 31:0 */
} _icp_icp_qgic2_gicd_icpendr1;

typedef union{
    _icp_icp_qgic2_gicd_icpendr1 bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QGIC2_GICD_ICPENDR1;

typedef struct{
    unsigned  INT : 32; /* 31:0 */
} _icp_icp_qgic2_gicd_icpendr2;

typedef union{
    _icp_icp_qgic2_gicd_icpendr2 bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QGIC2_GICD_ICPENDR2;

typedef struct{
    unsigned  INT : 32; /* 31:0 */
} _icp_icp_qgic2_gicd_isactiver0;

typedef union{
    _icp_icp_qgic2_gicd_isactiver0 bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QGIC2_GICD_ISACTIVER0;

typedef struct{
    unsigned  INT : 32; /* 31:0 */
} _icp_icp_qgic2_gicd_isactiver1;

typedef union{
    _icp_icp_qgic2_gicd_isactiver1 bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QGIC2_GICD_ISACTIVER1;

typedef struct{
    unsigned  INT : 32; /* 31:0 */
} _icp_icp_qgic2_gicd_isactiver2;

typedef union{
    _icp_icp_qgic2_gicd_isactiver2 bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QGIC2_GICD_ISACTIVER2;

typedef struct{
    unsigned  INT : 32; /* 31:0 */
} _icp_icp_qgic2_gicd_icactiver0;

typedef union{
    _icp_icp_qgic2_gicd_icactiver0 bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QGIC2_GICD_ICACTIVER0;

typedef struct{
    unsigned  INT : 32; /* 31:0 */
} _icp_icp_qgic2_gicd_icactiver1;

typedef union{
    _icp_icp_qgic2_gicd_icactiver1 bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QGIC2_GICD_ICACTIVER1;

typedef struct{
    unsigned  INT : 32; /* 31:0 */
} _icp_icp_qgic2_gicd_icactiver2;

typedef union{
    _icp_icp_qgic2_gicd_icactiver2 bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QGIC2_GICD_ICACTIVER2;

typedef struct{
    unsigned  UNUSED0 : 3; /* 2:0 */
    unsigned  INT0 : 5; /* 7:3 */
    unsigned  UNUSED1 : 3; /* 10:8 */
    unsigned  INT1 : 5; /* 15:11 */
    unsigned  UNUSED2 : 3; /* 18:16 */
    unsigned  INT2 : 5; /* 23:19 */
    unsigned  UNUSED3 : 3; /* 26:24 */
    unsigned  INT3 : 5; /* 31:27 */
} _icp_icp_qgic2_gicd_ipriorityr0;

typedef union{
    _icp_icp_qgic2_gicd_ipriorityr0 bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QGIC2_GICD_IPRIORITYR0;

typedef struct{
    unsigned  UNUSED0 : 3; /* 2:0 */
    unsigned  INT0 : 5; /* 7:3 */
    unsigned  UNUSED1 : 3; /* 10:8 */
    unsigned  INT1 : 5; /* 15:11 */
    unsigned  UNUSED2 : 3; /* 18:16 */
    unsigned  INT2 : 5; /* 23:19 */
    unsigned  UNUSED3 : 3; /* 26:24 */
    unsigned  INT3 : 5; /* 31:27 */
} _icp_icp_qgic2_gicd_ipriorityr1;

typedef union{
    _icp_icp_qgic2_gicd_ipriorityr1 bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QGIC2_GICD_IPRIORITYR1;

typedef struct{
    unsigned  UNUSED0 : 3; /* 2:0 */
    unsigned  INT0 : 5; /* 7:3 */
    unsigned  UNUSED1 : 3; /* 10:8 */
    unsigned  INT1 : 5; /* 15:11 */
    unsigned  UNUSED2 : 3; /* 18:16 */
    unsigned  INT2 : 5; /* 23:19 */
    unsigned  UNUSED3 : 3; /* 26:24 */
    unsigned  INT3 : 5; /* 31:27 */
} _icp_icp_qgic2_gicd_ipriorityr2;

typedef union{
    _icp_icp_qgic2_gicd_ipriorityr2 bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QGIC2_GICD_IPRIORITYR2;

typedef struct{
    unsigned  UNUSED0 : 3; /* 2:0 */
    unsigned  INT0 : 5; /* 7:3 */
    unsigned  UNUSED1 : 3; /* 10:8 */
    unsigned  INT1 : 5; /* 15:11 */
    unsigned  UNUSED2 : 3; /* 18:16 */
    unsigned  INT2 : 5; /* 23:19 */
    unsigned  UNUSED3 : 3; /* 26:24 */
    unsigned  INT3 : 5; /* 31:27 */
} _icp_icp_qgic2_gicd_ipriorityr3;

typedef union{
    _icp_icp_qgic2_gicd_ipriorityr3 bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QGIC2_GICD_IPRIORITYR3;

typedef struct{
    unsigned  UNUSED0 : 3; /* 2:0 */
    unsigned  INT0 : 5; /* 7:3 */
    unsigned  UNUSED1 : 3; /* 10:8 */
    unsigned  INT1 : 5; /* 15:11 */
    unsigned  UNUSED2 : 3; /* 18:16 */
    unsigned  INT2 : 5; /* 23:19 */
    unsigned  UNUSED3 : 3; /* 26:24 */
    unsigned  INT3 : 5; /* 31:27 */
} _icp_icp_qgic2_gicd_ipriorityr4;

typedef union{
    _icp_icp_qgic2_gicd_ipriorityr4 bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QGIC2_GICD_IPRIORITYR4;

typedef struct{
    unsigned  UNUSED0 : 3; /* 2:0 */
    unsigned  INT0 : 5; /* 7:3 */
    unsigned  UNUSED1 : 3; /* 10:8 */
    unsigned  INT1 : 5; /* 15:11 */
    unsigned  UNUSED2 : 3; /* 18:16 */
    unsigned  INT2 : 5; /* 23:19 */
    unsigned  UNUSED3 : 3; /* 26:24 */
    unsigned  INT3 : 5; /* 31:27 */
} _icp_icp_qgic2_gicd_ipriorityr5;

typedef union{
    _icp_icp_qgic2_gicd_ipriorityr5 bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QGIC2_GICD_IPRIORITYR5;

typedef struct{
    unsigned  UNUSED0 : 3; /* 2:0 */
    unsigned  INT0 : 5; /* 7:3 */
    unsigned  UNUSED1 : 3; /* 10:8 */
    unsigned  INT1 : 5; /* 15:11 */
    unsigned  UNUSED2 : 3; /* 18:16 */
    unsigned  INT2 : 5; /* 23:19 */
    unsigned  UNUSED3 : 3; /* 26:24 */
    unsigned  INT3 : 5; /* 31:27 */
} _icp_icp_qgic2_gicd_ipriorityr6;

typedef union{
    _icp_icp_qgic2_gicd_ipriorityr6 bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QGIC2_GICD_IPRIORITYR6;

typedef struct{
    unsigned  UNUSED0 : 3; /* 2:0 */
    unsigned  INT0 : 5; /* 7:3 */
    unsigned  UNUSED1 : 3; /* 10:8 */
    unsigned  INT1 : 5; /* 15:11 */
    unsigned  UNUSED2 : 3; /* 18:16 */
    unsigned  INT2 : 5; /* 23:19 */
    unsigned  UNUSED3 : 3; /* 26:24 */
    unsigned  INT3 : 5; /* 31:27 */
} _icp_icp_qgic2_gicd_ipriorityr7;

typedef union{
    _icp_icp_qgic2_gicd_ipriorityr7 bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QGIC2_GICD_IPRIORITYR7;

typedef struct{
    unsigned  UNUSED0 : 3; /* 2:0 */
    unsigned  INT0 : 5; /* 7:3 */
    unsigned  UNUSED1 : 3; /* 10:8 */
    unsigned  INT1 : 5; /* 15:11 */
    unsigned  UNUSED2 : 3; /* 18:16 */
    unsigned  INT2 : 5; /* 23:19 */
    unsigned  UNUSED3 : 3; /* 26:24 */
    unsigned  INT3 : 5; /* 31:27 */
} _icp_icp_qgic2_gicd_ipriorityr8;

typedef union{
    _icp_icp_qgic2_gicd_ipriorityr8 bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QGIC2_GICD_IPRIORITYR8;

typedef struct{
    unsigned  UNUSED0 : 3; /* 2:0 */
    unsigned  INT0 : 5; /* 7:3 */
    unsigned  UNUSED1 : 3; /* 10:8 */
    unsigned  INT1 : 5; /* 15:11 */
    unsigned  UNUSED2 : 3; /* 18:16 */
    unsigned  INT2 : 5; /* 23:19 */
    unsigned  UNUSED3 : 3; /* 26:24 */
    unsigned  INT3 : 5; /* 31:27 */
} _icp_icp_qgic2_gicd_ipriorityr9;

typedef union{
    _icp_icp_qgic2_gicd_ipriorityr9 bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QGIC2_GICD_IPRIORITYR9;

typedef struct{
    unsigned  UNUSED0 : 3; /* 2:0 */
    unsigned  INT0 : 5; /* 7:3 */
    unsigned  UNUSED1 : 3; /* 10:8 */
    unsigned  INT1 : 5; /* 15:11 */
    unsigned  UNUSED2 : 3; /* 18:16 */
    unsigned  INT2 : 5; /* 23:19 */
    unsigned  UNUSED3 : 3; /* 26:24 */
    unsigned  INT3 : 5; /* 31:27 */
} _icp_icp_qgic2_gicd_ipriorityr10;

typedef union{
    _icp_icp_qgic2_gicd_ipriorityr10 bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QGIC2_GICD_IPRIORITYR10;

typedef struct{
    unsigned  UNUSED0 : 3; /* 2:0 */
    unsigned  INT0 : 5; /* 7:3 */
    unsigned  UNUSED1 : 3; /* 10:8 */
    unsigned  INT1 : 5; /* 15:11 */
    unsigned  UNUSED2 : 3; /* 18:16 */
    unsigned  INT2 : 5; /* 23:19 */
    unsigned  UNUSED3 : 3; /* 26:24 */
    unsigned  INT3 : 5; /* 31:27 */
} _icp_icp_qgic2_gicd_ipriorityr11;

typedef union{
    _icp_icp_qgic2_gicd_ipriorityr11 bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QGIC2_GICD_IPRIORITYR11;

typedef struct{
    unsigned  UNUSED0 : 3; /* 2:0 */
    unsigned  INT0 : 5; /* 7:3 */
    unsigned  UNUSED1 : 3; /* 10:8 */
    unsigned  INT1 : 5; /* 15:11 */
    unsigned  UNUSED2 : 3; /* 18:16 */
    unsigned  INT2 : 5; /* 23:19 */
    unsigned  UNUSED3 : 3; /* 26:24 */
    unsigned  INT3 : 5; /* 31:27 */
} _icp_icp_qgic2_gicd_ipriorityr12;

typedef union{
    _icp_icp_qgic2_gicd_ipriorityr12 bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QGIC2_GICD_IPRIORITYR12;

typedef struct{
    unsigned  UNUSED0 : 3; /* 2:0 */
    unsigned  INT0 : 5; /* 7:3 */
    unsigned  UNUSED1 : 3; /* 10:8 */
    unsigned  INT1 : 5; /* 15:11 */
    unsigned  UNUSED2 : 3; /* 18:16 */
    unsigned  INT2 : 5; /* 23:19 */
    unsigned  UNUSED3 : 3; /* 26:24 */
    unsigned  INT3 : 5; /* 31:27 */
} _icp_icp_qgic2_gicd_ipriorityr13;

typedef union{
    _icp_icp_qgic2_gicd_ipriorityr13 bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QGIC2_GICD_IPRIORITYR13;

typedef struct{
    unsigned  UNUSED0 : 3; /* 2:0 */
    unsigned  INT0 : 5; /* 7:3 */
    unsigned  UNUSED1 : 3; /* 10:8 */
    unsigned  INT1 : 5; /* 15:11 */
    unsigned  UNUSED2 : 3; /* 18:16 */
    unsigned  INT2 : 5; /* 23:19 */
    unsigned  UNUSED3 : 3; /* 26:24 */
    unsigned  INT3 : 5; /* 31:27 */
} _icp_icp_qgic2_gicd_ipriorityr14;

typedef union{
    _icp_icp_qgic2_gicd_ipriorityr14 bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QGIC2_GICD_IPRIORITYR14;

typedef struct{
    unsigned  UNUSED0 : 3; /* 2:0 */
    unsigned  INT0 : 5; /* 7:3 */
    unsigned  UNUSED1 : 3; /* 10:8 */
    unsigned  INT1 : 5; /* 15:11 */
    unsigned  UNUSED2 : 3; /* 18:16 */
    unsigned  INT2 : 5; /* 23:19 */
    unsigned  UNUSED3 : 3; /* 26:24 */
    unsigned  INT3 : 5; /* 31:27 */
} _icp_icp_qgic2_gicd_ipriorityr15;

typedef union{
    _icp_icp_qgic2_gicd_ipriorityr15 bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QGIC2_GICD_IPRIORITYR15;

typedef struct{
    unsigned  UNUSED0 : 3; /* 2:0 */
    unsigned  INT0 : 5; /* 7:3 */
    unsigned  UNUSED1 : 3; /* 10:8 */
    unsigned  INT1 : 5; /* 15:11 */
    unsigned  UNUSED2 : 3; /* 18:16 */
    unsigned  INT2 : 5; /* 23:19 */
    unsigned  UNUSED3 : 3; /* 26:24 */
    unsigned  INT3 : 5; /* 31:27 */
} _icp_icp_qgic2_gicd_ipriorityr16;

typedef union{
    _icp_icp_qgic2_gicd_ipriorityr16 bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QGIC2_GICD_IPRIORITYR16;

typedef struct{
    unsigned  UNUSED0 : 3; /* 2:0 */
    unsigned  INT0 : 5; /* 7:3 */
    unsigned  UNUSED1 : 3; /* 10:8 */
    unsigned  INT1 : 5; /* 15:11 */
    unsigned  UNUSED2 : 3; /* 18:16 */
    unsigned  INT2 : 5; /* 23:19 */
    unsigned  UNUSED3 : 3; /* 26:24 */
    unsigned  INT3 : 5; /* 31:27 */
} _icp_icp_qgic2_gicd_ipriorityr17;

typedef union{
    _icp_icp_qgic2_gicd_ipriorityr17 bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QGIC2_GICD_IPRIORITYR17;

typedef struct{
    unsigned  UNUSED0 : 3; /* 2:0 */
    unsigned  INT0 : 5; /* 7:3 */
    unsigned  UNUSED1 : 3; /* 10:8 */
    unsigned  INT1 : 5; /* 15:11 */
    unsigned  UNUSED2 : 3; /* 18:16 */
    unsigned  INT2 : 5; /* 23:19 */
    unsigned  UNUSED3 : 3; /* 26:24 */
    unsigned  INT3 : 5; /* 31:27 */
} _icp_icp_qgic2_gicd_ipriorityr18;

typedef union{
    _icp_icp_qgic2_gicd_ipriorityr18 bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QGIC2_GICD_IPRIORITYR18;

typedef struct{
    unsigned  UNUSED0 : 3; /* 2:0 */
    unsigned  INT0 : 5; /* 7:3 */
    unsigned  UNUSED1 : 3; /* 10:8 */
    unsigned  INT1 : 5; /* 15:11 */
    unsigned  UNUSED2 : 3; /* 18:16 */
    unsigned  INT2 : 5; /* 23:19 */
    unsigned  UNUSED3 : 3; /* 26:24 */
    unsigned  INT3 : 5; /* 31:27 */
} _icp_icp_qgic2_gicd_ipriorityr19;

typedef union{
    _icp_icp_qgic2_gicd_ipriorityr19 bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QGIC2_GICD_IPRIORITYR19;

typedef struct{
    unsigned  UNUSED0 : 3; /* 2:0 */
    unsigned  INT0 : 5; /* 7:3 */
    unsigned  UNUSED1 : 3; /* 10:8 */
    unsigned  INT1 : 5; /* 15:11 */
    unsigned  UNUSED2 : 3; /* 18:16 */
    unsigned  INT2 : 5; /* 23:19 */
    unsigned  UNUSED3 : 3; /* 26:24 */
    unsigned  INT3 : 5; /* 31:27 */
} _icp_icp_qgic2_gicd_ipriorityr20;

typedef union{
    _icp_icp_qgic2_gicd_ipriorityr20 bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QGIC2_GICD_IPRIORITYR20;

typedef struct{
    unsigned  UNUSED0 : 3; /* 2:0 */
    unsigned  INT0 : 5; /* 7:3 */
    unsigned  UNUSED1 : 3; /* 10:8 */
    unsigned  INT1 : 5; /* 15:11 */
    unsigned  UNUSED2 : 3; /* 18:16 */
    unsigned  INT2 : 5; /* 23:19 */
    unsigned  UNUSED3 : 3; /* 26:24 */
    unsigned  INT3 : 5; /* 31:27 */
} _icp_icp_qgic2_gicd_ipriorityr21;

typedef union{
    _icp_icp_qgic2_gicd_ipriorityr21 bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QGIC2_GICD_IPRIORITYR21;

typedef struct{
    unsigned  UNUSED0 : 3; /* 2:0 */
    unsigned  INT0 : 5; /* 7:3 */
    unsigned  UNUSED1 : 3; /* 10:8 */
    unsigned  INT1 : 5; /* 15:11 */
    unsigned  UNUSED2 : 3; /* 18:16 */
    unsigned  INT2 : 5; /* 23:19 */
    unsigned  UNUSED3 : 3; /* 26:24 */
    unsigned  INT3 : 5; /* 31:27 */
} _icp_icp_qgic2_gicd_ipriorityr22;

typedef union{
    _icp_icp_qgic2_gicd_ipriorityr22 bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QGIC2_GICD_IPRIORITYR22;

typedef struct{
    unsigned  UNUSED0 : 3; /* 2:0 */
    unsigned  INT0 : 5; /* 7:3 */
    unsigned  UNUSED1 : 3; /* 10:8 */
    unsigned  INT1 : 5; /* 15:11 */
    unsigned  UNUSED2 : 3; /* 18:16 */
    unsigned  INT2 : 5; /* 23:19 */
    unsigned  UNUSED3 : 3; /* 26:24 */
    unsigned  INT3 : 5; /* 31:27 */
} _icp_icp_qgic2_gicd_ipriorityr23;

typedef union{
    _icp_icp_qgic2_gicd_ipriorityr23 bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QGIC2_GICD_IPRIORITYR23;

typedef struct{
    unsigned  INT0 : 8; /* 7:0 */
    unsigned  INT1 : 8; /* 15:8 */
    unsigned  INT2 : 8; /* 23:16 */
    unsigned  INT3 : 8; /* 31:24 */
} _icp_icp_qgic2_gicd_itargetsr0;

typedef union{
    _icp_icp_qgic2_gicd_itargetsr0 bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QGIC2_GICD_ITARGETSR0;

typedef struct{
    unsigned  INT0 : 8; /* 7:0 */
    unsigned  INT1 : 8; /* 15:8 */
    unsigned  INT2 : 8; /* 23:16 */
    unsigned  INT3 : 8; /* 31:24 */
} _icp_icp_qgic2_gicd_itargetsr1;

typedef union{
    _icp_icp_qgic2_gicd_itargetsr1 bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QGIC2_GICD_ITARGETSR1;

typedef struct{
    unsigned  INT0 : 8; /* 7:0 */
    unsigned  INT1 : 8; /* 15:8 */
    unsigned  INT2 : 8; /* 23:16 */
    unsigned  INT3 : 8; /* 31:24 */
} _icp_icp_qgic2_gicd_itargetsr2;

typedef union{
    _icp_icp_qgic2_gicd_itargetsr2 bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QGIC2_GICD_ITARGETSR2;

typedef struct{
    unsigned  INT0 : 8; /* 7:0 */
    unsigned  INT1 : 8; /* 15:8 */
    unsigned  INT2 : 8; /* 23:16 */
    unsigned  INT3 : 8; /* 31:24 */
} _icp_icp_qgic2_gicd_itargetsr3;

typedef union{
    _icp_icp_qgic2_gicd_itargetsr3 bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QGIC2_GICD_ITARGETSR3;

typedef struct{
    unsigned  INT0 : 8; /* 7:0 */
    unsigned  INT1 : 8; /* 15:8 */
    unsigned  INT2 : 8; /* 23:16 */
    unsigned  INT3 : 8; /* 31:24 */
} _icp_icp_qgic2_gicd_itargetsr4;

typedef union{
    _icp_icp_qgic2_gicd_itargetsr4 bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QGIC2_GICD_ITARGETSR4;

typedef struct{
    unsigned  INT0 : 8; /* 7:0 */
    unsigned  INT1 : 8; /* 15:8 */
    unsigned  INT2 : 8; /* 23:16 */
    unsigned  INT3 : 8; /* 31:24 */
} _icp_icp_qgic2_gicd_itargetsr5;

typedef union{
    _icp_icp_qgic2_gicd_itargetsr5 bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QGIC2_GICD_ITARGETSR5;

typedef struct{
    unsigned  INT0 : 8; /* 7:0 */
    unsigned  INT1 : 8; /* 15:8 */
    unsigned  INT2 : 8; /* 23:16 */
    unsigned  INT3 : 8; /* 31:24 */
} _icp_icp_qgic2_gicd_itargetsr6;

typedef union{
    _icp_icp_qgic2_gicd_itargetsr6 bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QGIC2_GICD_ITARGETSR6;

typedef struct{
    unsigned  INT0 : 8; /* 7:0 */
    unsigned  INT1 : 8; /* 15:8 */
    unsigned  INT2 : 8; /* 23:16 */
    unsigned  INT3 : 8; /* 31:24 */
} _icp_icp_qgic2_gicd_itargetsr7;

typedef union{
    _icp_icp_qgic2_gicd_itargetsr7 bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QGIC2_GICD_ITARGETSR7;

typedef struct{
    unsigned  INT0 : 8; /* 7:0 */
    unsigned  INT1 : 8; /* 15:8 */
    unsigned  INT2 : 8; /* 23:16 */
    unsigned  INT3 : 8; /* 31:24 */
} _icp_icp_qgic2_gicd_itargetsr8;

typedef union{
    _icp_icp_qgic2_gicd_itargetsr8 bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QGIC2_GICD_ITARGETSR8;

typedef struct{
    unsigned  INT0 : 8; /* 7:0 */
    unsigned  INT1 : 8; /* 15:8 */
    unsigned  INT2 : 8; /* 23:16 */
    unsigned  INT3 : 8; /* 31:24 */
} _icp_icp_qgic2_gicd_itargetsr9;

typedef union{
    _icp_icp_qgic2_gicd_itargetsr9 bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QGIC2_GICD_ITARGETSR9;

typedef struct{
    unsigned  INT0 : 8; /* 7:0 */
    unsigned  INT1 : 8; /* 15:8 */
    unsigned  INT2 : 8; /* 23:16 */
    unsigned  INT3 : 8; /* 31:24 */
} _icp_icp_qgic2_gicd_itargetsr10;

typedef union{
    _icp_icp_qgic2_gicd_itargetsr10 bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QGIC2_GICD_ITARGETSR10;

typedef struct{
    unsigned  INT0 : 8; /* 7:0 */
    unsigned  INT1 : 8; /* 15:8 */
    unsigned  INT2 : 8; /* 23:16 */
    unsigned  INT3 : 8; /* 31:24 */
} _icp_icp_qgic2_gicd_itargetsr11;

typedef union{
    _icp_icp_qgic2_gicd_itargetsr11 bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QGIC2_GICD_ITARGETSR11;

typedef struct{
    unsigned  INT0 : 8; /* 7:0 */
    unsigned  INT1 : 8; /* 15:8 */
    unsigned  INT2 : 8; /* 23:16 */
    unsigned  INT3 : 8; /* 31:24 */
} _icp_icp_qgic2_gicd_itargetsr12;

typedef union{
    _icp_icp_qgic2_gicd_itargetsr12 bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QGIC2_GICD_ITARGETSR12;

typedef struct{
    unsigned  INT0 : 8; /* 7:0 */
    unsigned  INT1 : 8; /* 15:8 */
    unsigned  INT2 : 8; /* 23:16 */
    unsigned  INT3 : 8; /* 31:24 */
} _icp_icp_qgic2_gicd_itargetsr13;

typedef union{
    _icp_icp_qgic2_gicd_itargetsr13 bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QGIC2_GICD_ITARGETSR13;

typedef struct{
    unsigned  INT0 : 8; /* 7:0 */
    unsigned  INT1 : 8; /* 15:8 */
    unsigned  INT2 : 8; /* 23:16 */
    unsigned  INT3 : 8; /* 31:24 */
} _icp_icp_qgic2_gicd_itargetsr14;

typedef union{
    _icp_icp_qgic2_gicd_itargetsr14 bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QGIC2_GICD_ITARGETSR14;

typedef struct{
    unsigned  INT0 : 8; /* 7:0 */
    unsigned  INT1 : 8; /* 15:8 */
    unsigned  INT2 : 8; /* 23:16 */
    unsigned  INT3 : 8; /* 31:24 */
} _icp_icp_qgic2_gicd_itargetsr15;

typedef union{
    _icp_icp_qgic2_gicd_itargetsr15 bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QGIC2_GICD_ITARGETSR15;

typedef struct{
    unsigned  INT0 : 8; /* 7:0 */
    unsigned  INT1 : 8; /* 15:8 */
    unsigned  INT2 : 8; /* 23:16 */
    unsigned  INT3 : 8; /* 31:24 */
} _icp_icp_qgic2_gicd_itargetsr16;

typedef union{
    _icp_icp_qgic2_gicd_itargetsr16 bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QGIC2_GICD_ITARGETSR16;

typedef struct{
    unsigned  INT0 : 8; /* 7:0 */
    unsigned  INT1 : 8; /* 15:8 */
    unsigned  INT2 : 8; /* 23:16 */
    unsigned  INT3 : 8; /* 31:24 */
} _icp_icp_qgic2_gicd_itargetsr17;

typedef union{
    _icp_icp_qgic2_gicd_itargetsr17 bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QGIC2_GICD_ITARGETSR17;

typedef struct{
    unsigned  INT0 : 8; /* 7:0 */
    unsigned  INT1 : 8; /* 15:8 */
    unsigned  INT2 : 8; /* 23:16 */
    unsigned  INT3 : 8; /* 31:24 */
} _icp_icp_qgic2_gicd_itargetsr18;

typedef union{
    _icp_icp_qgic2_gicd_itargetsr18 bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QGIC2_GICD_ITARGETSR18;

typedef struct{
    unsigned  INT0 : 8; /* 7:0 */
    unsigned  INT1 : 8; /* 15:8 */
    unsigned  INT2 : 8; /* 23:16 */
    unsigned  INT3 : 8; /* 31:24 */
} _icp_icp_qgic2_gicd_itargetsr19;

typedef union{
    _icp_icp_qgic2_gicd_itargetsr19 bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QGIC2_GICD_ITARGETSR19;

typedef struct{
    unsigned  INT0 : 8; /* 7:0 */
    unsigned  INT1 : 8; /* 15:8 */
    unsigned  INT2 : 8; /* 23:16 */
    unsigned  INT3 : 8; /* 31:24 */
} _icp_icp_qgic2_gicd_itargetsr20;

typedef union{
    _icp_icp_qgic2_gicd_itargetsr20 bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QGIC2_GICD_ITARGETSR20;

typedef struct{
    unsigned  INT0 : 8; /* 7:0 */
    unsigned  INT1 : 8; /* 15:8 */
    unsigned  INT2 : 8; /* 23:16 */
    unsigned  INT3 : 8; /* 31:24 */
} _icp_icp_qgic2_gicd_itargetsr21;

typedef union{
    _icp_icp_qgic2_gicd_itargetsr21 bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QGIC2_GICD_ITARGETSR21;

typedef struct{
    unsigned  INT0 : 8; /* 7:0 */
    unsigned  INT1 : 8; /* 15:8 */
    unsigned  INT2 : 8; /* 23:16 */
    unsigned  INT3 : 8; /* 31:24 */
} _icp_icp_qgic2_gicd_itargetsr22;

typedef union{
    _icp_icp_qgic2_gicd_itargetsr22 bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QGIC2_GICD_ITARGETSR22;

typedef struct{
    unsigned  INT0 : 8; /* 7:0 */
    unsigned  INT1 : 8; /* 15:8 */
    unsigned  INT2 : 8; /* 23:16 */
    unsigned  INT3 : 8; /* 31:24 */
} _icp_icp_qgic2_gicd_itargetsr23;

typedef union{
    _icp_icp_qgic2_gicd_itargetsr23 bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QGIC2_GICD_ITARGETSR23;

typedef struct{
    unsigned  INT0 : 2; /* 1:0 */
    unsigned  INT1 : 2; /* 3:2 */
    unsigned  INT2 : 2; /* 5:4 */
    unsigned  INT3 : 2; /* 7:6 */
    unsigned  INT4 : 2; /* 9:8 */
    unsigned  INT5 : 2; /* 11:10 */
    unsigned  INT6 : 2; /* 13:12 */
    unsigned  INT7 : 2; /* 15:14 */
    unsigned  INT8 : 2; /* 17:16 */
    unsigned  INT9 : 2; /* 19:18 */
    unsigned  INT10 : 2; /* 21:20 */
    unsigned  INT11 : 2; /* 23:22 */
    unsigned  INT12 : 2; /* 25:24 */
    unsigned  INT13 : 2; /* 27:26 */
    unsigned  INT14 : 2; /* 29:28 */
    unsigned  INT15 : 2; /* 31:30 */
} _icp_icp_qgic2_gicd_icfgr0;

typedef union{
    _icp_icp_qgic2_gicd_icfgr0 bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QGIC2_GICD_ICFGR0;

typedef struct{
    unsigned  INT0 : 2; /* 1:0 */
    unsigned  INT1 : 2; /* 3:2 */
    unsigned  INT2 : 2; /* 5:4 */
    unsigned  INT3 : 2; /* 7:6 */
    unsigned  INT4 : 2; /* 9:8 */
    unsigned  INT5 : 2; /* 11:10 */
    unsigned  INT6 : 2; /* 13:12 */
    unsigned  INT7 : 2; /* 15:14 */
    unsigned  INT8 : 2; /* 17:16 */
    unsigned  INT9 : 2; /* 19:18 */
    unsigned  INT10 : 2; /* 21:20 */
    unsigned  INT11 : 2; /* 23:22 */
    unsigned  INT12 : 2; /* 25:24 */
    unsigned  INT13 : 2; /* 27:26 */
    unsigned  INT14 : 2; /* 29:28 */
    unsigned  INT15 : 2; /* 31:30 */
} _icp_icp_qgic2_gicd_icfgr1;

typedef union{
    _icp_icp_qgic2_gicd_icfgr1 bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QGIC2_GICD_ICFGR1;

typedef struct{
    unsigned  INT0 : 2; /* 1:0 */
    unsigned  INT1 : 2; /* 3:2 */
    unsigned  INT2 : 2; /* 5:4 */
    unsigned  INT3 : 2; /* 7:6 */
    unsigned  INT4 : 2; /* 9:8 */
    unsigned  INT5 : 2; /* 11:10 */
    unsigned  INT6 : 2; /* 13:12 */
    unsigned  INT7 : 2; /* 15:14 */
    unsigned  INT8 : 2; /* 17:16 */
    unsigned  INT9 : 2; /* 19:18 */
    unsigned  INT10 : 2; /* 21:20 */
    unsigned  INT11 : 2; /* 23:22 */
    unsigned  INT12 : 2; /* 25:24 */
    unsigned  INT13 : 2; /* 27:26 */
    unsigned  INT14 : 2; /* 29:28 */
    unsigned  INT15 : 2; /* 31:30 */
} _icp_icp_qgic2_gicd_icfgr2;

typedef union{
    _icp_icp_qgic2_gicd_icfgr2 bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QGIC2_GICD_ICFGR2;

typedef struct{
    unsigned  INT0 : 2; /* 1:0 */
    unsigned  INT1 : 2; /* 3:2 */
    unsigned  INT2 : 2; /* 5:4 */
    unsigned  INT3 : 2; /* 7:6 */
    unsigned  INT4 : 2; /* 9:8 */
    unsigned  INT5 : 2; /* 11:10 */
    unsigned  INT6 : 2; /* 13:12 */
    unsigned  INT7 : 2; /* 15:14 */
    unsigned  INT8 : 2; /* 17:16 */
    unsigned  INT9 : 2; /* 19:18 */
    unsigned  INT10 : 2; /* 21:20 */
    unsigned  INT11 : 2; /* 23:22 */
    unsigned  INT12 : 2; /* 25:24 */
    unsigned  INT13 : 2; /* 27:26 */
    unsigned  INT14 : 2; /* 29:28 */
    unsigned  INT15 : 2; /* 31:30 */
} _icp_icp_qgic2_gicd_icfgr3;

typedef union{
    _icp_icp_qgic2_gicd_icfgr3 bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QGIC2_GICD_ICFGR3;

typedef struct{
    unsigned  INT0 : 2; /* 1:0 */
    unsigned  INT1 : 2; /* 3:2 */
    unsigned  INT2 : 2; /* 5:4 */
    unsigned  INT3 : 2; /* 7:6 */
    unsigned  INT4 : 2; /* 9:8 */
    unsigned  INT5 : 2; /* 11:10 */
    unsigned  INT6 : 2; /* 13:12 */
    unsigned  INT7 : 2; /* 15:14 */
    unsigned  INT8 : 2; /* 17:16 */
    unsigned  INT9 : 2; /* 19:18 */
    unsigned  INT10 : 2; /* 21:20 */
    unsigned  INT11 : 2; /* 23:22 */
    unsigned  INT12 : 2; /* 25:24 */
    unsigned  INT13 : 2; /* 27:26 */
    unsigned  INT14 : 2; /* 29:28 */
    unsigned  INT15 : 2; /* 31:30 */
} _icp_icp_qgic2_gicd_icfgr4;

typedef union{
    _icp_icp_qgic2_gicd_icfgr4 bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QGIC2_GICD_ICFGR4;

typedef struct{
    unsigned  INT0 : 2; /* 1:0 */
    unsigned  INT1 : 2; /* 3:2 */
    unsigned  INT2 : 2; /* 5:4 */
    unsigned  INT3 : 2; /* 7:6 */
    unsigned  INT4 : 2; /* 9:8 */
    unsigned  INT5 : 2; /* 11:10 */
    unsigned  INT6 : 2; /* 13:12 */
    unsigned  INT7 : 2; /* 15:14 */
    unsigned  INT8 : 2; /* 17:16 */
    unsigned  INT9 : 2; /* 19:18 */
    unsigned  INT10 : 2; /* 21:20 */
    unsigned  INT11 : 2; /* 23:22 */
    unsigned  INT12 : 2; /* 25:24 */
    unsigned  INT13 : 2; /* 27:26 */
    unsigned  INT14 : 2; /* 29:28 */
    unsigned  INT15 : 2; /* 31:30 */
} _icp_icp_qgic2_gicd_icfgr5;

typedef union{
    _icp_icp_qgic2_gicd_icfgr5 bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QGIC2_GICD_ICFGR5;

typedef struct{
    unsigned  INT_ID : 4; /* 3:0 */
    unsigned  UNUSED0 : 11; /* 14:4 */
    unsigned  SATT : 1; /* 15:15 */
    unsigned  T_LIST : 8; /* 23:16 */
    unsigned  T_FILTER : 2; /* 25:24 */
    unsigned  UNUSED1 : 6; /* 31:26 */
} _icp_icp_qgic2_gicd_sgir;

typedef union{
    _icp_icp_qgic2_gicd_sgir bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QGIC2_GICD_SGIR;

typedef struct{
    unsigned  SGI0 : 8; /* 7:0 */
    unsigned  SGI1 : 8; /* 15:8 */
    unsigned  SGI2 : 8; /* 23:16 */
    unsigned  SGI3 : 8; /* 31:24 */
} _icp_icp_qgic2_gicd_cpendsgir0;

typedef union{
    _icp_icp_qgic2_gicd_cpendsgir0 bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QGIC2_GICD_CPENDSGIR0;

typedef struct{
    unsigned  SGI0 : 8; /* 7:0 */
    unsigned  SGI1 : 8; /* 15:8 */
    unsigned  SGI2 : 8; /* 23:16 */
    unsigned  SGI3 : 8; /* 31:24 */
} _icp_icp_qgic2_gicd_cpendsgir1;

typedef union{
    _icp_icp_qgic2_gicd_cpendsgir1 bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QGIC2_GICD_CPENDSGIR1;

typedef struct{
    unsigned  SGI0 : 8; /* 7:0 */
    unsigned  SGI1 : 8; /* 15:8 */
    unsigned  SGI2 : 8; /* 23:16 */
    unsigned  SGI3 : 8; /* 31:24 */
} _icp_icp_qgic2_gicd_cpendsgir2;

typedef union{
    _icp_icp_qgic2_gicd_cpendsgir2 bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QGIC2_GICD_CPENDSGIR2;

typedef struct{
    unsigned  SGI0 : 8; /* 7:0 */
    unsigned  SGI1 : 8; /* 15:8 */
    unsigned  SGI2 : 8; /* 23:16 */
    unsigned  SGI3 : 8; /* 31:24 */
} _icp_icp_qgic2_gicd_cpendsgir3;

typedef union{
    _icp_icp_qgic2_gicd_cpendsgir3 bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QGIC2_GICD_CPENDSGIR3;

typedef struct{
    unsigned  SGI0 : 8; /* 7:0 */
    unsigned  SGI1 : 8; /* 15:8 */
    unsigned  SGI2 : 8; /* 23:16 */
    unsigned  SGI3 : 8; /* 31:24 */
} _icp_icp_qgic2_gicd_spendsgir0;

typedef union{
    _icp_icp_qgic2_gicd_spendsgir0 bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QGIC2_GICD_SPENDSGIR0;

typedef struct{
    unsigned  SGI0 : 8; /* 7:0 */
    unsigned  SGI1 : 8; /* 15:8 */
    unsigned  SGI2 : 8; /* 23:16 */
    unsigned  SGI3 : 8; /* 31:24 */
} _icp_icp_qgic2_gicd_spendsgir1;

typedef union{
    _icp_icp_qgic2_gicd_spendsgir1 bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QGIC2_GICD_SPENDSGIR1;

typedef struct{
    unsigned  SGI0 : 8; /* 7:0 */
    unsigned  SGI1 : 8; /* 15:8 */
    unsigned  SGI2 : 8; /* 23:16 */
    unsigned  SGI3 : 8; /* 31:24 */
} _icp_icp_qgic2_gicd_spendsgir2;

typedef union{
    _icp_icp_qgic2_gicd_spendsgir2 bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QGIC2_GICD_SPENDSGIR2;

typedef struct{
    unsigned  SGI0 : 8; /* 7:0 */
    unsigned  SGI1 : 8; /* 15:8 */
    unsigned  SGI2 : 8; /* 23:16 */
    unsigned  SGI3 : 8; /* 31:24 */
} _icp_icp_qgic2_gicd_spendsgir3;

typedef union{
    _icp_icp_qgic2_gicd_spendsgir3 bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QGIC2_GICD_SPENDSGIR3;

typedef struct{
    unsigned  PART_NUM : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _icp_icp_qgic2_gicd_pidr0;

typedef union{
    _icp_icp_qgic2_gicd_pidr0 bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QGIC2_GICD_PIDR0;

typedef struct{
    unsigned  PART_NUM : 4; /* 3:0 */
    unsigned  DESIGNER : 4; /* 7:4 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _icp_icp_qgic2_gicd_pidr1;

typedef union{
    _icp_icp_qgic2_gicd_pidr1 bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QGIC2_GICD_PIDR1;

typedef struct{
    unsigned  DESIGNER : 3; /* 2:0 */
    unsigned  USES_JEP_CODE : 1; /* 3:3 */
    unsigned  ARCH_VERSION : 4; /* 7:4 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _icp_icp_qgic2_gicd_pidr2;

typedef union{
    _icp_icp_qgic2_gicd_pidr2 bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QGIC2_GICD_PIDR2;

typedef struct{
    unsigned  UNUSED0 : 4; /* 3:0 */
    unsigned  REVISION : 4; /* 7:4 */
    unsigned  UNUSED1 : 24; /* 31:8 */
} _icp_icp_qgic2_gicd_pidr3;

typedef union{
    _icp_icp_qgic2_gicd_pidr3 bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QGIC2_GICD_PIDR3;

typedef struct{
    unsigned  DESIGNER : 4; /* 3:0 */
    unsigned  UNUSED0 : 28; /* 31:4 */
} _icp_icp_qgic2_gicd_pidr4;

typedef union{
    _icp_icp_qgic2_gicd_pidr4 bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QGIC2_GICD_PIDR4;

typedef struct{
    unsigned  RESRVD_BY_ARM : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _icp_icp_qgic2_gicd_pidr5;

typedef union{
    _icp_icp_qgic2_gicd_pidr5 bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QGIC2_GICD_PIDR5;

typedef struct{
    unsigned  RESRVD_BY_ARM : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _icp_icp_qgic2_gicd_pidr6;

typedef union{
    _icp_icp_qgic2_gicd_pidr6 bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QGIC2_GICD_PIDR6;

typedef struct{
    unsigned  RESRVD_BY_ARM : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _icp_icp_qgic2_gicd_pidr7;

typedef union{
    _icp_icp_qgic2_gicd_pidr7 bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QGIC2_GICD_PIDR7;

typedef struct{
    unsigned  COMP_ID_0 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _icp_icp_qgic2_gicd_cidr0;

typedef union{
    _icp_icp_qgic2_gicd_cidr0 bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QGIC2_GICD_CIDR0;

typedef struct{
    unsigned  COMP_ID_1 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _icp_icp_qgic2_gicd_cidr1;

typedef union{
    _icp_icp_qgic2_gicd_cidr1 bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QGIC2_GICD_CIDR1;

typedef struct{
    unsigned  COMP_ID_2 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _icp_icp_qgic2_gicd_cidr2;

typedef union{
    _icp_icp_qgic2_gicd_cidr2 bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QGIC2_GICD_CIDR2;

typedef struct{
    unsigned  COMP_ID_3 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _icp_icp_qgic2_gicd_cidr3;

typedef union{
    _icp_icp_qgic2_gicd_cidr3 bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QGIC2_GICD_CIDR3;

typedef struct{
    unsigned  EN : 1; /* 0:0 */
    unsigned  UIE : 1; /* 1:1 */
    unsigned  SKIDIE : 1; /* 2:2 */
    unsigned  NPIE : 1; /* 3:3 */
    unsigned  VEG0IE : 1; /* 4:4 */
    unsigned  VDG0IE : 1; /* 5:5 */
    unsigned  VEG1IE : 1; /* 6:6 */
    unsigned  VDG1IE : 1; /* 7:7 */
    unsigned  UNUSED0 : 19; /* 26:8 */
    unsigned  EOICOUNT : 5; /* 31:27 */
} _icp_icp_qgic2_gich_hcr;

typedef union{
    _icp_icp_qgic2_gich_hcr bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QGIC2_GICH_HCR;

typedef struct{
    unsigned  LISTREGS : 6; /* 5:0 */
    unsigned  UNUSED0 : 20; /* 25:6 */
    unsigned  PREBITS : 3; /* 28:26 */
    unsigned  PRIBITS : 3; /* 31:29 */
} _icp_icp_qgic2_gich_vtr;

typedef union{
    _icp_icp_qgic2_gich_vtr bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QGIC2_GICH_VTR;

typedef struct{
    unsigned  VMENABLE_G0 : 1; /* 0:0 */
    unsigned  VMENABLE_G1 : 1; /* 1:1 */
    unsigned  VMACKCTL : 1; /* 2:2 */
    unsigned  VMFIQEN : 1; /* 3:3 */
    unsigned  VMGBPR : 1; /* 4:4 */
    unsigned  UNUSED0 : 4; /* 8:5 */
    unsigned  VEM : 1; /* 9:9 */
    unsigned  UNUSED1 : 8; /* 17:10 */
    unsigned  VMG1BP : 3; /* 20:18 */
    unsigned  VMG0BP : 3; /* 23:21 */
    unsigned  UNUSED2 : 3; /* 26:24 */
    unsigned  VMPMR : 5; /* 31:27 */
} _icp_icp_qgic2_gich_vmcr;

typedef union{
    _icp_icp_qgic2_gich_vmcr bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QGIC2_GICH_VMCR;

typedef struct{
    unsigned  EI : 1; /* 0:0 */
    unsigned  UI : 1; /* 1:1 */
    unsigned  SKIDI : 1; /* 2:2 */
    unsigned  NPI : 1; /* 3:3 */
    unsigned  VESI : 1; /* 4:4 */
    unsigned  VDSI : 1; /* 5:5 */
    unsigned  VENSI : 1; /* 6:6 */
    unsigned  VDNSI : 1; /* 7:7 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _icp_icp_qgic2_gich_misr;

typedef union{
    _icp_icp_qgic2_gich_misr bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QGIC2_GICH_MISR;

typedef struct{
    unsigned  LR : 4; /* 3:0 */
    unsigned  UNUSED0 : 28; /* 31:4 */
} _icp_icp_qgic2_gich_eisr;

typedef union{
    _icp_icp_qgic2_gich_eisr bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QGIC2_GICH_EISR;

typedef struct{
    unsigned  LR : 4; /* 3:0 */
    unsigned  UNUSED0 : 28; /* 31:4 */
} _icp_icp_qgic2_gich_elrsr;

typedef union{
    _icp_icp_qgic2_gich_elrsr bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QGIC2_GICH_ELRSR;

typedef struct{
    unsigned  PRI : 32; /* 31:0 */
} _icp_icp_qgic2_gich_apr;

typedef union{
    _icp_icp_qgic2_gich_apr bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QGIC2_GICH_APR;

typedef struct{
    unsigned  VIRTL_ID : 10; /* 9:0 */
    unsigned  PHY_ID : 10; /* 19:10 */
    unsigned  UNUSED0 : 3; /* 22:20 */
    unsigned  PRI : 5; /* 27:23 */
    unsigned  STATE : 2; /* 29:28 */
    unsigned  GRP : 1; /* 30:30 */
    unsigned  HW : 1; /* 31:31 */
} _icp_icp_qgic2_gich_lr0;

typedef union{
    _icp_icp_qgic2_gich_lr0 bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QGIC2_GICH_LR0;

typedef struct{
    unsigned  VIRTL_ID : 10; /* 9:0 */
    unsigned  PHY_ID : 10; /* 19:10 */
    unsigned  UNUSED0 : 3; /* 22:20 */
    unsigned  PRI : 5; /* 27:23 */
    unsigned  STATE : 2; /* 29:28 */
    unsigned  GRP : 1; /* 30:30 */
    unsigned  HW : 1; /* 31:31 */
} _icp_icp_qgic2_gich_lr1;

typedef union{
    _icp_icp_qgic2_gich_lr1 bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QGIC2_GICH_LR1;

typedef struct{
    unsigned  VIRTL_ID : 10; /* 9:0 */
    unsigned  PHY_ID : 10; /* 19:10 */
    unsigned  UNUSED0 : 3; /* 22:20 */
    unsigned  PRI : 5; /* 27:23 */
    unsigned  STATE : 2; /* 29:28 */
    unsigned  GRP : 1; /* 30:30 */
    unsigned  HW : 1; /* 31:31 */
} _icp_icp_qgic2_gich_lr2;

typedef union{
    _icp_icp_qgic2_gich_lr2 bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QGIC2_GICH_LR2;

typedef struct{
    unsigned  VIRTL_ID : 10; /* 9:0 */
    unsigned  PHY_ID : 10; /* 19:10 */
    unsigned  UNUSED0 : 3; /* 22:20 */
    unsigned  PRI : 5; /* 27:23 */
    unsigned  STATE : 2; /* 29:28 */
    unsigned  GRP : 1; /* 30:30 */
    unsigned  HW : 1; /* 31:31 */
} _icp_icp_qgic2_gich_lr3;

typedef union{
    _icp_icp_qgic2_gich_lr3 bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QGIC2_GICH_LR3;

typedef struct{
    unsigned  UNUSED0 : 10; /* 9:0 */
    unsigned  CPUID : 3; /* 12:10 */
    unsigned  UNUSED1 : 6; /* 18:13 */
    unsigned  EI : 1; /* 19:19 */
    unsigned  UNUSED2 : 12; /* 31:20 */
} _icp_icp_qgic2_gich_sw_lr;

typedef union{
    _icp_icp_qgic2_gich_sw_lr bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QGIC2_GICH_SW_LR;

typedef struct{
    unsigned  ENABLE : 1; /* 0:0 */
    unsigned  ENABLE_NS : 1; /* 1:1 */
    unsigned  ACKCTL : 1; /* 2:2 */
    unsigned  S_DEST : 1; /* 3:3 */
    unsigned  SBPR : 1; /* 4:4 */
    unsigned  FIQBYPDISABLE : 1; /* 5:5 */
    unsigned  IRQBYPDISABLE : 1; /* 6:6 */
    unsigned  FIQBYPDISABLENS : 1; /* 7:7 */
    unsigned  IRQBYPDISABLENS : 1; /* 8:8 */
    unsigned  EOIMODE : 1; /* 9:9 */
    unsigned  EOIMODENS : 1; /* 10:10 */
    unsigned  UNUSED0 : 21; /* 31:11 */
} _icp_icp_qgic2_gicc_ctlr;

typedef union{
    _icp_icp_qgic2_gicc_ctlr bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QGIC2_GICC_CTLR;

typedef struct{
    unsigned  UNUSED0 : 3; /* 2:0 */
    unsigned  LEVEL : 5; /* 7:3 */
    unsigned  UNUSED1 : 24; /* 31:8 */
} _icp_icp_qgic2_gicc_pmr;

typedef union{
    _icp_icp_qgic2_gicc_pmr bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QGIC2_GICC_PMR;

typedef struct{
    unsigned  VAL : 3; /* 2:0 */
    unsigned  UNUSED0 : 29; /* 31:3 */
} _icp_icp_qgic2_gicc_bpr;

typedef union{
    _icp_icp_qgic2_gicc_bpr bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QGIC2_GICC_BPR;

typedef struct{
    unsigned  INT_ID : 10; /* 9:0 */
    unsigned  CPU_ID : 3; /* 12:10 */
    unsigned  UNUSED0 : 19; /* 31:13 */
} _icp_icp_qgic2_gicc_iar;

typedef union{
    _icp_icp_qgic2_gicc_iar bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QGIC2_GICC_IAR;

typedef struct{
    unsigned  INT_ID : 10; /* 9:0 */
    unsigned  CPU_ID : 3; /* 12:10 */
    unsigned  UNUSED0 : 19; /* 31:13 */
} _icp_icp_qgic2_gicc_eoir;

typedef union{
    _icp_icp_qgic2_gicc_eoir bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QGIC2_GICC_EOIR;

typedef struct{
    unsigned  UNUSED0 : 3; /* 2:0 */
    unsigned  VAL : 5; /* 7:3 */
    unsigned  UNUSED1 : 24; /* 31:8 */
} _icp_icp_qgic2_gicc_rpr;

typedef union{
    _icp_icp_qgic2_gicc_rpr bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QGIC2_GICC_RPR;

typedef struct{
    unsigned  INT_ID : 10; /* 9:0 */
    unsigned  CPU_ID : 3; /* 12:10 */
    unsigned  UNUSED0 : 19; /* 31:13 */
} _icp_icp_qgic2_gicc_hppir;

typedef union{
    _icp_icp_qgic2_gicc_hppir bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QGIC2_GICC_HPPIR;

typedef struct{
    unsigned  VAL : 3; /* 2:0 */
    unsigned  UNUSED0 : 29; /* 31:3 */
} _icp_icp_qgic2_gicc_abpr;

typedef union{
    _icp_icp_qgic2_gicc_abpr bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QGIC2_GICC_ABPR;

typedef struct{
    unsigned  INT_ID : 10; /* 9:0 */
    unsigned  CPU_ID : 3; /* 12:10 */
    unsigned  UNUSED0 : 19; /* 31:13 */
} _icp_icp_qgic2_gicc_aiar;

typedef union{
    _icp_icp_qgic2_gicc_aiar bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QGIC2_GICC_AIAR;

typedef struct{
    unsigned  INT_ID : 10; /* 9:0 */
    unsigned  CPU_ID : 3; /* 12:10 */
    unsigned  UNUSED0 : 19; /* 31:13 */
} _icp_icp_qgic2_gicc_aeoir;

typedef union{
    _icp_icp_qgic2_gicc_aeoir bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QGIC2_GICC_AEOIR;

typedef struct{
    unsigned  INT_ID : 10; /* 9:0 */
    unsigned  CPU_ID : 3; /* 12:10 */
    unsigned  UNUSED0 : 19; /* 31:13 */
} _icp_icp_qgic2_gicc_ahppir;

typedef union{
    _icp_icp_qgic2_gicc_ahppir bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QGIC2_GICC_AHPPIR;

typedef struct{
    unsigned  PRI : 32; /* 31:0 */
} _icp_icp_qgic2_gicc_apr;

typedef union{
    _icp_icp_qgic2_gicc_apr bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QGIC2_GICC_APR;

typedef struct{
    unsigned  PRI : 32; /* 31:0 */
} _icp_icp_qgic2_gicc_nsapr;

typedef union{
    _icp_icp_qgic2_gicc_nsapr bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QGIC2_GICC_NSAPR;

typedef struct{
    unsigned  IMPLEMENTOR : 12; /* 11:0 */
    unsigned  REVISION : 4; /* 15:12 */
    unsigned  ARCH_VERSION : 4; /* 19:16 */
    unsigned  PART_NUM : 12; /* 31:20 */
} _icp_icp_qgic2_gicc_iidr;

typedef union{
    _icp_icp_qgic2_gicc_iidr bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QGIC2_GICC_IIDR;

typedef struct{
    unsigned  INT_ID : 10; /* 9:0 */
    unsigned  CPU_ID : 3; /* 12:10 */
    unsigned  UNUSED0 : 19; /* 31:13 */
} _icp_icp_qgic2_gicc_dir;

typedef union{
    _icp_icp_qgic2_gicc_dir bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QGIC2_GICC_DIR;

typedef struct{
    unsigned  ENABLE_G0 : 1; /* 0:0 */
    unsigned  ENABLE_G1 : 1; /* 1:1 */
    unsigned  ACKCTL : 1; /* 2:2 */
    unsigned  FIQEN : 1; /* 3:3 */
    unsigned  GBPR : 1; /* 4:4 */
    unsigned  UNUSED0 : 4; /* 8:5 */
    unsigned  EOIMODE : 1; /* 9:9 */
    unsigned  UNUSED1 : 22; /* 31:10 */
} _icp_icp_qgic2_gicv_ctlr;

typedef union{
    _icp_icp_qgic2_gicv_ctlr bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QGIC2_GICV_CTLR;

typedef struct{
    unsigned  UNUSED0 : 3; /* 2:0 */
    unsigned  LEVEL : 5; /* 7:3 */
    unsigned  UNUSED1 : 24; /* 31:8 */
} _icp_icp_qgic2_gicv_pmr;

typedef union{
    _icp_icp_qgic2_gicv_pmr bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QGIC2_GICV_PMR;

typedef struct{
    unsigned  VAL : 3; /* 2:0 */
    unsigned  UNUSED0 : 29; /* 31:3 */
} _icp_icp_qgic2_gicv_bpr;

typedef union{
    _icp_icp_qgic2_gicv_bpr bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QGIC2_GICV_BPR;

typedef struct{
    unsigned  INT_ID : 10; /* 9:0 */
    unsigned  CPU_ID : 3; /* 12:10 */
    unsigned  UNUSED0 : 19; /* 31:13 */
} _icp_icp_qgic2_gicv_iar;

typedef union{
    _icp_icp_qgic2_gicv_iar bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QGIC2_GICV_IAR;

typedef struct{
    unsigned  INT_ID : 10; /* 9:0 */
    unsigned  CPU_ID : 3; /* 12:10 */
    unsigned  UNUSED0 : 19; /* 31:13 */
} _icp_icp_qgic2_gicv_eoir;

typedef union{
    _icp_icp_qgic2_gicv_eoir bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QGIC2_GICV_EOIR;

typedef struct{
    unsigned  UNUSED0 : 3; /* 2:0 */
    unsigned  VAL : 5; /* 7:3 */
    unsigned  UNUSED1 : 24; /* 31:8 */
} _icp_icp_qgic2_gicv_rpr;

typedef union{
    _icp_icp_qgic2_gicv_rpr bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QGIC2_GICV_RPR;

typedef struct{
    unsigned  INT_ID : 10; /* 9:0 */
    unsigned  CPU_ID : 3; /* 12:10 */
    unsigned  UNUSED0 : 19; /* 31:13 */
} _icp_icp_qgic2_gicv_hppir;

typedef union{
    _icp_icp_qgic2_gicv_hppir bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QGIC2_GICV_HPPIR;

typedef struct{
    unsigned  VAL : 3; /* 2:0 */
    unsigned  UNUSED0 : 29; /* 31:3 */
} _icp_icp_qgic2_gicv_abpr;

typedef union{
    _icp_icp_qgic2_gicv_abpr bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QGIC2_GICV_ABPR;

typedef struct{
    unsigned  INT_ID : 10; /* 9:0 */
    unsigned  CPU_ID : 3; /* 12:10 */
    unsigned  UNUSED0 : 19; /* 31:13 */
} _icp_icp_qgic2_gicv_aiar;

typedef union{
    _icp_icp_qgic2_gicv_aiar bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QGIC2_GICV_AIAR;

typedef struct{
    unsigned  INT_ID : 10; /* 9:0 */
    unsigned  CPU_ID : 3; /* 12:10 */
    unsigned  UNUSED0 : 19; /* 31:13 */
} _icp_icp_qgic2_gicv_aeoir;

typedef union{
    _icp_icp_qgic2_gicv_aeoir bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QGIC2_GICV_AEOIR;

typedef struct{
    unsigned  INT_ID : 10; /* 9:0 */
    unsigned  CPU_ID : 3; /* 12:10 */
    unsigned  UNUSED0 : 19; /* 31:13 */
} _icp_icp_qgic2_gicv_ahppir;

typedef union{
    _icp_icp_qgic2_gicv_ahppir bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QGIC2_GICV_AHPPIR;

typedef struct{
    unsigned  PRI : 32; /* 31:0 */
} _icp_icp_qgic2_gicv_apr;

typedef union{
    _icp_icp_qgic2_gicv_apr bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QGIC2_GICV_APR;

typedef struct{
    unsigned  IMPLEMENTOR : 12; /* 11:0 */
    unsigned  REVISION : 4; /* 15:12 */
    unsigned  ARCH_VERSION : 4; /* 19:16 */
    unsigned  PART_NUM : 12; /* 31:20 */
} _icp_icp_qgic2_gicv_iidr;

typedef union{
    _icp_icp_qgic2_gicv_iidr bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QGIC2_GICV_IIDR;

typedef struct{
    unsigned  INT_ID : 10; /* 9:0 */
    unsigned  CPU_ID : 3; /* 12:10 */
    unsigned  UNUSED0 : 19; /* 31:13 */
} _icp_icp_qgic2_gicv_dir;

typedef union{
    _icp_icp_qgic2_gicv_dir bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QGIC2_GICV_DIR;

typedef struct{
    unsigned  CNTFRQ : 32; /* 31:0 */
} _icp_icp_qtmr_qtmr_ac_cntfrq;

typedef union{
    _icp_icp_qtmr_qtmr_ac_cntfrq bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QTMR_QTMR_AC_CNTFRQ;

typedef struct{
    unsigned  NSN : 2; /* 1:0 */
    unsigned  UNUSED0 : 30; /* 31:2 */
} _icp_icp_qtmr_qtmr_ac_cntnsar_fg0;

typedef union{
    _icp_icp_qtmr_qtmr_ac_cntnsar_fg0 bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QTMR_QTMR_AC_CNTNSAR_FG0;

typedef struct{
    unsigned  F0_CFG : 4; /* 3:0 */
    unsigned  F1_CFG : 4; /* 7:4 */
    unsigned  F2_CFG : 4; /* 11:8 */
    unsigned  F3_CFG : 4; /* 15:12 */
    unsigned  F4_CFG : 4; /* 19:16 */
    unsigned  F5_CFG : 4; /* 23:20 */
    unsigned  F6_CFG : 4; /* 27:24 */
    unsigned  F7_CFG : 4; /* 31:28 */
} _icp_icp_qtmr_qtmr_ac_cnttidr_fg0;

typedef union{
    _icp_icp_qtmr_qtmr_ac_cnttidr_fg0 bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QTMR_QTMR_AC_CNTTIDR_FG0;

typedef struct{
    unsigned  RPCT : 1; /* 0:0 */
    unsigned  RPVCT : 1; /* 1:1 */
    unsigned  RFRQ : 1; /* 2:2 */
    unsigned  RVOFF : 1; /* 3:3 */
    unsigned  RWVT : 1; /* 4:4 */
    unsigned  RWPT : 1; /* 5:5 */
    unsigned  UNUSED0 : 26; /* 31:6 */
} _icp_icp_qtmr_qtmr_ac_cntacr0_fg0;

typedef union{
    _icp_icp_qtmr_qtmr_ac_cntacr0_fg0 bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QTMR_QTMR_AC_CNTACR0_FG0;

typedef struct{
    unsigned  RPCT : 1; /* 0:0 */
    unsigned  RPVCT : 1; /* 1:1 */
    unsigned  RFRQ : 1; /* 2:2 */
    unsigned  RVOFF : 1; /* 3:3 */
    unsigned  RWVT : 1; /* 4:4 */
    unsigned  RWPT : 1; /* 5:5 */
    unsigned  UNUSED0 : 26; /* 31:6 */
} _icp_icp_qtmr_qtmr_ac_cntacr1_fg0;

typedef union{
    _icp_icp_qtmr_qtmr_ac_cntacr1_fg0 bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QTMR_QTMR_AC_CNTACR1_FG0;

typedef struct{
    unsigned  CNTVOFF_LO : 32; /* 31:0 */
} _icp_icp_qtmr_qtmr_ac_cntvoff_fg0_lo_0;

typedef union{
    _icp_icp_qtmr_qtmr_ac_cntvoff_fg0_lo_0 bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QTMR_QTMR_AC_CNTVOFF_FG0_LO_0;

typedef struct{
    unsigned  CNTVOFF_HI : 24; /* 23:0 */
    unsigned  UNUSED0 : 8; /* 31:24 */
} _icp_icp_qtmr_qtmr_ac_cntvoff_fg0_hi_0;

typedef union{
    _icp_icp_qtmr_qtmr_ac_cntvoff_fg0_hi_0 bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QTMR_QTMR_AC_CNTVOFF_FG0_HI_0;

typedef struct{
    unsigned  CNTVOFF_LO : 32; /* 31:0 */
} _icp_icp_qtmr_qtmr_ac_cntvoff_fg0_lo_1;

typedef union{
    _icp_icp_qtmr_qtmr_ac_cntvoff_fg0_lo_1 bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QTMR_QTMR_AC_CNTVOFF_FG0_LO_1;

typedef struct{
    unsigned  CNTVOFF_HI : 24; /* 23:0 */
    unsigned  UNUSED0 : 8; /* 31:24 */
} _icp_icp_qtmr_qtmr_ac_cntvoff_fg0_hi_1;

typedef union{
    _icp_icp_qtmr_qtmr_ac_cntvoff_fg0_hi_1 bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QTMR_QTMR_AC_CNTVOFF_FG0_HI_1;

typedef struct{
    unsigned  TEST_BUS_EN : 1; /* 0:0 */
    unsigned  DSBL_ATOMIC : 1; /* 1:1 */
    unsigned  UNUSED0 : 30; /* 31:2 */
} _icp_icp_qtmr_qtmr_ac_cfg;

typedef union{
    _icp_icp_qtmr_qtmr_ac_cfg bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QTMR_QTMR_AC_CFG;

typedef struct{
    unsigned  STEP : 16; /* 15:0 */
    unsigned  MINOR : 12; /* 27:16 */
    unsigned  MAJOR : 4; /* 31:28 */
} _icp_icp_qtmr_qtmr_ac_version;

typedef union{
    _icp_icp_qtmr_qtmr_ac_version bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QTMR_QTMR_AC_VERSION;

typedef struct{
    unsigned  HW_FRAME_SEL1 : 32; /* 31:0 */
} _icp_icp_qtmr_qtmr_ac_hw_frame_sel_1;

typedef union{
    _icp_icp_qtmr_qtmr_ac_hw_frame_sel_1 bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QTMR_QTMR_AC_HW_FRAME_SEL_1;

typedef struct{
    unsigned  HW_FRAME_SEL2 : 32; /* 31:0 */
} _icp_icp_qtmr_qtmr_ac_hw_frame_sel_2;

typedef union{
    _icp_icp_qtmr_qtmr_ac_hw_frame_sel_2 bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QTMR_QTMR_AC_HW_FRAME_SEL_2;

typedef struct{
    unsigned  CNTPCT_LO : 32; /* 31:0 */
} _icp_icp_qtmr_qtmr_v1_cntpct_lo;

typedef union{
    _icp_icp_qtmr_qtmr_v1_cntpct_lo bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QTMR_QTMR_V1_CNTPCT_LO;

typedef struct{
    unsigned  CNTPCT_HI : 24; /* 23:0 */
    unsigned  UNUSED0 : 8; /* 31:24 */
} _icp_icp_qtmr_qtmr_v1_cntpct_hi;

typedef union{
    _icp_icp_qtmr_qtmr_v1_cntpct_hi bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QTMR_QTMR_V1_CNTPCT_HI;

typedef struct{
    unsigned  CNTVCT_LO : 32; /* 31:0 */
} _icp_icp_qtmr_qtmr_v1_cntvct_lo;

typedef union{
    _icp_icp_qtmr_qtmr_v1_cntvct_lo bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QTMR_QTMR_V1_CNTVCT_LO;

typedef struct{
    unsigned  CNTVCT_HI : 24; /* 23:0 */
    unsigned  UNUSED0 : 8; /* 31:24 */
} _icp_icp_qtmr_qtmr_v1_cntvct_hi;

typedef union{
    _icp_icp_qtmr_qtmr_v1_cntvct_hi bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QTMR_QTMR_V1_CNTVCT_HI;

typedef struct{
    unsigned  CNTFRQ : 32; /* 31:0 */
} _icp_icp_qtmr_qtmr_v1_cntfrq;

typedef union{
    _icp_icp_qtmr_qtmr_v1_cntfrq bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QTMR_QTMR_V1_CNTFRQ;

typedef struct{
    unsigned  PL0PCTEN : 1; /* 0:0 */
    unsigned  PL0VCTEN : 1; /* 1:1 */
    unsigned  UNUSED0 : 6; /* 7:2 */
    unsigned  PL0VTEN : 1; /* 8:8 */
    unsigned  PL0CTEN : 1; /* 9:9 */
    unsigned  UNUSED1 : 22; /* 31:10 */
} _icp_icp_qtmr_qtmr_v1_cntpl0acr;

typedef union{
    _icp_icp_qtmr_qtmr_v1_cntpl0acr bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QTMR_QTMR_V1_CNTPL0ACR;

typedef struct{
    unsigned  CNTVOFF_L0 : 32; /* 31:0 */
} _icp_icp_qtmr_qtmr_v1_cntvoff_lo;

typedef union{
    _icp_icp_qtmr_qtmr_v1_cntvoff_lo bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QTMR_QTMR_V1_CNTVOFF_LO;

typedef struct{
    unsigned  CNTVOFF_HI : 24; /* 23:0 */
    unsigned  UNUSED0 : 8; /* 31:24 */
} _icp_icp_qtmr_qtmr_v1_cntvoff_hi;

typedef union{
    _icp_icp_qtmr_qtmr_v1_cntvoff_hi bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QTMR_QTMR_V1_CNTVOFF_HI;

typedef struct{
    unsigned  CNTP_CVAL_L0 : 32; /* 31:0 */
} _icp_icp_qtmr_qtmr_v1_cntp_cval_lo;

typedef union{
    _icp_icp_qtmr_qtmr_v1_cntp_cval_lo bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QTMR_QTMR_V1_CNTP_CVAL_LO;

typedef struct{
    unsigned  CNTP_CVAL_HI : 24; /* 23:0 */
    unsigned  UNUSED0 : 8; /* 31:24 */
} _icp_icp_qtmr_qtmr_v1_cntp_cval_hi;

typedef union{
    _icp_icp_qtmr_qtmr_v1_cntp_cval_hi bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QTMR_QTMR_V1_CNTP_CVAL_HI;

typedef struct{
    unsigned  CNTP_TVAL : 32; /* 31:0 */
} _icp_icp_qtmr_qtmr_v1_cntp_tval;

typedef union{
    _icp_icp_qtmr_qtmr_v1_cntp_tval bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QTMR_QTMR_V1_CNTP_TVAL;

typedef struct{
    unsigned  EN : 1; /* 0:0 */
    unsigned  IMSK : 1; /* 1:1 */
    unsigned  ISTAT : 1; /* 2:2 */
    unsigned  UNUSED0 : 29; /* 31:3 */
} _icp_icp_qtmr_qtmr_v1_cntp_ctl;

typedef union{
    _icp_icp_qtmr_qtmr_v1_cntp_ctl bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QTMR_QTMR_V1_CNTP_CTL;

typedef struct{
    unsigned  CNTV_CVAL_L0 : 32; /* 31:0 */
} _icp_icp_qtmr_qtmr_v1_cntv_cval_lo;

typedef union{
    _icp_icp_qtmr_qtmr_v1_cntv_cval_lo bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QTMR_QTMR_V1_CNTV_CVAL_LO;

typedef struct{
    unsigned  CNTV_CVAL_HI : 24; /* 23:0 */
    unsigned  UNUSED0 : 8; /* 31:24 */
} _icp_icp_qtmr_qtmr_v1_cntv_cval_hi;

typedef union{
    _icp_icp_qtmr_qtmr_v1_cntv_cval_hi bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QTMR_QTMR_V1_CNTV_CVAL_HI;

typedef struct{
    unsigned  CNTV_TVAL : 32; /* 31:0 */
} _icp_icp_qtmr_qtmr_v1_cntv_tval;

typedef union{
    _icp_icp_qtmr_qtmr_v1_cntv_tval bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QTMR_QTMR_V1_CNTV_TVAL;

typedef struct{
    unsigned  EN : 1; /* 0:0 */
    unsigned  IMSK : 1; /* 1:1 */
    unsigned  ISTAT : 1; /* 2:2 */
    unsigned  UNUSED0 : 29; /* 31:3 */
} _icp_icp_qtmr_qtmr_v1_cntv_ctl;

typedef union{
    _icp_icp_qtmr_qtmr_v1_cntv_ctl bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QTMR_QTMR_V1_CNTV_CTL;

typedef struct{
    unsigned  STEP : 16; /* 15:0 */
    unsigned  MINOR : 12; /* 27:16 */
    unsigned  MAJOR : 4; /* 31:28 */
} _icp_icp_qtmr_qtmr_v1_version;

typedef union{
    _icp_icp_qtmr_qtmr_v1_version bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QTMR_QTMR_V1_VERSION;

typedef struct{
    unsigned  CNTPCT_LO : 32; /* 31:0 */
} _icp_icp_qtmr_qtmr_v2_cntpct_lo;

typedef union{
    _icp_icp_qtmr_qtmr_v2_cntpct_lo bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QTMR_QTMR_V2_CNTPCT_LO;

typedef struct{
    unsigned  CNTPCT_HI : 24; /* 23:0 */
    unsigned  UNUSED0 : 8; /* 31:24 */
} _icp_icp_qtmr_qtmr_v2_cntpct_hi;

typedef union{
    _icp_icp_qtmr_qtmr_v2_cntpct_hi bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QTMR_QTMR_V2_CNTPCT_HI;

typedef struct{
    unsigned  CNTVCT_LO : 32; /* 31:0 */
} _icp_icp_qtmr_qtmr_v2_cntvct_lo;

typedef union{
    _icp_icp_qtmr_qtmr_v2_cntvct_lo bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QTMR_QTMR_V2_CNTVCT_LO;

typedef struct{
    unsigned  CNTVCT_HI : 24; /* 23:0 */
    unsigned  UNUSED0 : 8; /* 31:24 */
} _icp_icp_qtmr_qtmr_v2_cntvct_hi;

typedef union{
    _icp_icp_qtmr_qtmr_v2_cntvct_hi bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QTMR_QTMR_V2_CNTVCT_HI;

typedef struct{
    unsigned  CNTFRQ : 32; /* 31:0 */
} _icp_icp_qtmr_qtmr_v2_cntfrq;

typedef union{
    _icp_icp_qtmr_qtmr_v2_cntfrq bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QTMR_QTMR_V2_CNTFRQ;

typedef struct{
    unsigned  CNTP_CVAL_L0 : 32; /* 31:0 */
} _icp_icp_qtmr_qtmr_v2_cntp_cval_lo;

typedef union{
    _icp_icp_qtmr_qtmr_v2_cntp_cval_lo bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QTMR_QTMR_V2_CNTP_CVAL_LO;

typedef struct{
    unsigned  CNTP_CVAL_HI : 24; /* 23:0 */
    unsigned  UNUSED0 : 8; /* 31:24 */
} _icp_icp_qtmr_qtmr_v2_cntp_cval_hi;

typedef union{
    _icp_icp_qtmr_qtmr_v2_cntp_cval_hi bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QTMR_QTMR_V2_CNTP_CVAL_HI;

typedef struct{
    unsigned  CNTP_TVAL : 32; /* 31:0 */
} _icp_icp_qtmr_qtmr_v2_cntp_tval;

typedef union{
    _icp_icp_qtmr_qtmr_v2_cntp_tval bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QTMR_QTMR_V2_CNTP_TVAL;

typedef struct{
    unsigned  EN : 1; /* 0:0 */
    unsigned  IMSK : 1; /* 1:1 */
    unsigned  ISTAT : 1; /* 2:2 */
    unsigned  UNUSED0 : 29; /* 31:3 */
} _icp_icp_qtmr_qtmr_v2_cntp_ctl;

typedef union{
    _icp_icp_qtmr_qtmr_v2_cntp_ctl bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QTMR_QTMR_V2_CNTP_CTL;

typedef struct{
    unsigned  CNTV_CVAL_L0 : 32; /* 31:0 */
} _icp_icp_qtmr_qtmr_v2_cntv_cval_lo;

typedef union{
    _icp_icp_qtmr_qtmr_v2_cntv_cval_lo bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QTMR_QTMR_V2_CNTV_CVAL_LO;

typedef struct{
    unsigned  CNTV_CVAL_HI : 24; /* 23:0 */
    unsigned  UNUSED0 : 8; /* 31:24 */
} _icp_icp_qtmr_qtmr_v2_cntv_cval_hi;

typedef union{
    _icp_icp_qtmr_qtmr_v2_cntv_cval_hi bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QTMR_QTMR_V2_CNTV_CVAL_HI;

typedef struct{
    unsigned  CNTV_TVAL : 32; /* 31:0 */
} _icp_icp_qtmr_qtmr_v2_cntv_tval;

typedef union{
    _icp_icp_qtmr_qtmr_v2_cntv_tval bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QTMR_QTMR_V2_CNTV_TVAL;

typedef struct{
    unsigned  EN : 1; /* 0:0 */
    unsigned  IMSK : 1; /* 1:1 */
    unsigned  ISTAT : 1; /* 2:2 */
    unsigned  UNUSED0 : 29; /* 31:3 */
} _icp_icp_qtmr_qtmr_v2_cntv_ctl;

typedef union{
    _icp_icp_qtmr_qtmr_v2_cntv_ctl bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QTMR_QTMR_V2_CNTV_CTL;

typedef struct{
    unsigned  STEP : 16; /* 15:0 */
    unsigned  MINOR : 12; /* 27:16 */
    unsigned  MAJOR : 4; /* 31:28 */
} _icp_icp_qtmr_qtmr_v2_version;

typedef union{
    _icp_icp_qtmr_qtmr_v2_version bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QTMR_QTMR_V2_VERSION;

typedef struct{
    unsigned  WDT_EN : 1; /* 0:0 */
    unsigned  WS0 : 1; /* 1:1 */
    unsigned  WS1 : 1; /* 2:2 */
    unsigned  WDT_FREEZE_EN : 1; /* 3:3 */
    unsigned  UNUSED0 : 28; /* 31:4 */
} _icp_icp_qtmr_qtmr_wdt_csr;

typedef union{
    _icp_icp_qtmr_qtmr_wdt_csr bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QTMR_QTMR_WDT_CSR;

typedef struct{
    unsigned  WDT_OFFSET : 32; /* 31:0 */
} _icp_icp_qtmr_qtmr_wdt_offset;

typedef union{
    _icp_icp_qtmr_qtmr_wdt_offset bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QTMR_QTMR_WDT_OFFSET;

typedef struct{
    unsigned  CVAL_LO : 32; /* 31:0 */
} _icp_icp_qtmr_qtmr_wdt_cval_lo;

typedef union{
    _icp_icp_qtmr_qtmr_wdt_cval_lo bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QTMR_QTMR_WDT_CVAL_LO;

typedef struct{
    unsigned  CVAL_HI : 24; /* 23:0 */
    unsigned  UNUSED0 : 8; /* 31:24 */
} _icp_icp_qtmr_qtmr_wdt_cval_hi;

typedef union{
    _icp_icp_qtmr_qtmr_wdt_cval_hi bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QTMR_QTMR_WDT_CVAL_HI;

typedef struct{
    unsigned  JEP_ID_CODE : 7; /* 6:0 */
    unsigned  UNUSED0 : 1; /* 7:7 */
    unsigned  JEP_CONT_CODE : 4; /* 11:8 */
    unsigned  IMPL_REV : 4; /* 15:12 */
    unsigned  ARCH_VERSION : 4; /* 19:16 */
    unsigned  PDT_ID : 12; /* 31:20 */
} _icp_icp_qtmr_qtmr_wdt_ctl_iidr;

typedef union{
    _icp_icp_qtmr_qtmr_wdt_ctl_iidr bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QTMR_QTMR_WDT_CTL_IIDR;

typedef struct{
    unsigned  STEP : 16; /* 15:0 */
    unsigned  MINOR : 12; /* 27:16 */
    unsigned  MAJOR : 4; /* 31:28 */
} _icp_icp_qtmr_qtmr_wdt_ctl_version;

typedef union{
    _icp_icp_qtmr_qtmr_wdt_ctl_version bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QTMR_QTMR_WDT_CTL_VERSION;

typedef struct{
    unsigned  PIDR_FLD1 : 4; /* 3:0 */
    unsigned  ARCH_REV : 4; /* 7:4 */
    unsigned  PIDR_FLD2 : 24; /* 31:8 */
} _icp_icp_qtmr_qtmr_wdt_ctl_pidr2;

typedef union{
    _icp_icp_qtmr_qtmr_wdt_ctl_pidr2 bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QTMR_QTMR_WDT_CTL_PIDR2;

typedef struct{
    unsigned  WRR : 32; /* 31:0 */
} _icp_icp_qtmr_qtmr_wdt_rr;

typedef union{
    _icp_icp_qtmr_qtmr_wdt_rr bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QTMR_QTMR_WDT_RR;

typedef struct{
    unsigned  JEP_ID_CODE : 7; /* 6:0 */
    unsigned  UNUSED0 : 1; /* 7:7 */
    unsigned  JEP_CONT_CODE : 4; /* 11:8 */
    unsigned  IMPL_REV : 4; /* 15:12 */
    unsigned  ARCH_VERSION : 4; /* 19:16 */
    unsigned  PDT_ID : 12; /* 31:20 */
} _icp_icp_qtmr_qtmr_wdt_ref_iidr;

typedef union{
    _icp_icp_qtmr_qtmr_wdt_ref_iidr bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QTMR_QTMR_WDT_REF_IIDR;

typedef struct{
    unsigned  STEP : 16; /* 15:0 */
    unsigned  MINOR : 12; /* 27:16 */
    unsigned  MAJOR : 4; /* 31:28 */
} _icp_icp_qtmr_qtmr_wdt_ref_version;

typedef union{
    _icp_icp_qtmr_qtmr_wdt_ref_version bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QTMR_QTMR_WDT_REF_VERSION;

typedef struct{
    unsigned  PIDR_FLD1 : 4; /* 3:0 */
    unsigned  ARCH_VERSION : 4; /* 7:4 */
    unsigned  PIDR_FLD2 : 24; /* 31:8 */
} _icp_icp_qtmr_qtmr_wdt_ref_pidr2;

typedef union{
    _icp_icp_qtmr_qtmr_wdt_ref_pidr2 bitfields,bits;
    unsigned int u32All;

} ICP_ICP_QTMR_QTMR_WDT_REF_PIDR2;

typedef struct{
    unsigned  STEP : 16; /* 15:0 */
    unsigned  MINOR : 12; /* 27:16 */
    unsigned  MAJOR : 4; /* 31:28 */
} _icp_icp_sierra_a5_hw_version;

typedef union{
    _icp_icp_sierra_a5_hw_version bitfields,bits;
    unsigned int u32All;

} ICP_ICP_SIERRA_A5_HW_VERSION;

typedef struct{
    unsigned  CSR_TIMER_RESET : 1; /* 0:0 */
    unsigned  CSR_QGIC_RESET : 1; /* 1:1 */
    unsigned  CSR_CPU_RESET : 1; /* 2:2 */
    unsigned  CSR_DBG_RESET : 1; /* 3:3 */
    unsigned  CSR_FUNC_RESET : 1; /* 4:4 */
    unsigned  UNUSED0 : 27; /* 31:5 */
} _icp_icp_sierra_a5_csr_nsec_reset;

typedef union{
    _icp_icp_sierra_a5_csr_nsec_reset bitfields,bits;
    unsigned int u32All;

} ICP_ICP_SIERRA_A5_CSR_NSEC_RESET;

typedef struct{
    unsigned  CSR_VINITHI : 1; /* 0:0 */
    unsigned  CSR_TEINIT : 1; /* 1:1 */
    unsigned  UNUSED0 : 1; /* 2:2 */
    unsigned  CSR_L1RSTDISABLE : 1; /* 3:3 */
    unsigned  CSR_WAKE_UP_EN : 1; /* 4:4 */
    unsigned  CSR_CFGEND : 1; /* 5:5 */
    unsigned  CSR_CP15SDISABLE : 1; /* 6:6 */
    unsigned  UNUSED1 : 2; /* 8:7 */
    unsigned  CSR_A5_CPU_EN : 1; /* 9:9 */
    unsigned  CSR_WDT_FREEZE : 1; /* 10:10 */
    unsigned  CSR_GEN_EVENT : 1; /* 11:11 */
    unsigned  CSR_EN_CLKGATE_WFI : 1; /* 12:12 */
    unsigned  CSR_EN_CLKGATE_WFE : 1; /* 13:13 */
    unsigned  CSR_EDBGRQ : 1; /* 14:14 */
    unsigned  UNUSED2 : 4; /* 18:15 */
    unsigned  CSR_TSMAXWIDTH : 1; /* 19:19 */
    unsigned  CSR_TSNATURAL : 1; /* 20:20 */
    unsigned  UNUSED3 : 1; /* 21:21 */
    unsigned  CSR_DBGSWENABLE : 1; /* 22:22 */
    unsigned  UNUSED4 : 9; /* 31:23 */
} _icp_icp_sierra_a5_csr_a5_control;

typedef union{
    _icp_icp_sierra_a5_csr_a5_control bitfields,bits;
    unsigned int u32All;

} ICP_ICP_SIERRA_A5_CSR_A5_CONTROL;

typedef struct{
    unsigned  CSR_ETM_MAXEXTIN : 3; /* 2:0 */
    unsigned  UNUSED0 : 1; /* 3:3 */
    unsigned  CSR_ETM_MAXEXTOUT : 2; /* 5:4 */
    unsigned  UNUSED1 : 2; /* 7:6 */
    unsigned  CSR_ETM_MAXCORES : 3; /* 10:8 */
    unsigned  UNUSED2 : 5; /* 15:11 */
    unsigned  CSR_ETMEN : 1; /* 16:16 */
    unsigned  CSR_ETMSTANDBYWFX : 1; /* 17:17 */
    unsigned  UNUSED3 : 14; /* 31:18 */
} _icp_icp_sierra_a5_csr_etm;

typedef union{
    _icp_icp_sierra_a5_csr_etm bitfields,bits;
    unsigned int u32All;

} ICP_ICP_SIERRA_A5_CSR_ETM;

typedef struct{
    unsigned  A2HOSTINTEN : 1; /* 0:0 */
    unsigned  WDT_WS0EN : 1; /* 1:1 */
    unsigned  WDT_WS1EN : 1; /* 2:2 */
    unsigned  UNUSED0 : 29; /* 31:3 */
} _icp_icp_sierra_a5_csr_a2hostinten;

typedef union{
    _icp_icp_sierra_a5_csr_a2hostinten bitfields,bits;
    unsigned int u32All;

} ICP_ICP_SIERRA_A5_CSR_A2HOSTINTEN;

typedef struct{
    unsigned  A2HOSTINT : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _icp_icp_sierra_a5_csr_a2hostint;

typedef union{
    _icp_icp_sierra_a5_csr_a2hostint bitfields,bits;
    unsigned int u32All;

} ICP_ICP_SIERRA_A5_CSR_A2HOSTINT;

typedef struct{
    unsigned  A2HOSTINTCLR : 1; /* 0:0 */
    unsigned  WDT_WS0ENCLR : 1; /* 1:1 */
    unsigned  WDT_WS1ENCLR : 1; /* 2:2 */
    unsigned  UNUSED0 : 29; /* 31:3 */
} _icp_icp_sierra_a5_csr_a2hostintclr;

typedef union{
    _icp_icp_sierra_a5_csr_a2hostintclr bitfields,bits;
    unsigned int u32All;

} ICP_ICP_SIERRA_A5_CSR_A2HOSTINTCLR;

typedef struct{
    unsigned  A2HOSTINT : 1; /* 0:0 */
    unsigned  WDT_WS0 : 1; /* 1:1 */
    unsigned  WDT_WS1 : 1; /* 2:2 */
    unsigned  UNUSED0 : 29; /* 31:3 */
} _icp_icp_sierra_a5_csr_a2hostintstatus;

typedef union{
    _icp_icp_sierra_a5_csr_a2hostintstatus bitfields,bits;
    unsigned int u32All;

} ICP_ICP_SIERRA_A5_CSR_A2HOSTINTSTATUS;

typedef struct{
    unsigned  A2HOSTINT : 1; /* 0:0 */
    unsigned  WDT_WS0 : 1; /* 1:1 */
    unsigned  WDT_WS1 : 1; /* 2:2 */
    unsigned  UNUSED0 : 29; /* 31:3 */
} _icp_icp_sierra_a5_csr_a2hostintset;

typedef union{
    _icp_icp_sierra_a5_csr_a2hostintset bitfields,bits;
    unsigned int u32All;

} ICP_ICP_SIERRA_A5_CSR_A2HOSTINTSET;

typedef struct{
    unsigned  HOSTINT : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _icp_icp_sierra_a5_csr_host2icpint;

typedef union{
    _icp_icp_sierra_a5_csr_host2icpint bitfields,bits;
    unsigned int u32All;

} ICP_ICP_SIERRA_A5_CSR_HOST2ICPINT;

typedef struct{
    unsigned  SYS_CACHE_MODE : 2; /* 1:0 */
    unsigned  UNUSED0 : 2; /* 3:2 */
    unsigned  SYS_CACHE_AR_OVERRIDE_EN : 1; /* 4:4 */
    unsigned  SYS_CACHE_AW_OVERRIDE_EN : 1; /* 5:5 */
    unsigned  UNUSED1 : 2; /* 7:6 */
    unsigned  SYS_CACHE_INDEX : 5; /* 12:8 */
    unsigned  SYS_CACHE_AR_MIN_FOOTPRINT : 1; /* 13:13 */
    unsigned  SYS_CACHE_AW_MIN_FOOTPRINT : 1; /* 14:14 */
    unsigned  UNUSED2 : 1; /* 15:15 */
    unsigned  SYS_CACHE_AW_CACHE_VALUE : 4; /* 19:16 */
    unsigned  SYS_CACHE_AR_CACHE_VALUE : 4; /* 23:20 */
    unsigned  UNUSED3 : 8; /* 31:24 */
} _icp_icp_sierra_a5_csr_sys_cache_ctrl;

typedef union{
    _icp_icp_sierra_a5_csr_sys_cache_ctrl bitfields,bits;
    unsigned int u32All;

} ICP_ICP_SIERRA_A5_CSR_SYS_CACHE_CTRL;

typedef struct{
    unsigned  AR_QOS : 4; /* 3:0 */
    unsigned  UNUSED0 : 4; /* 7:4 */
    unsigned  AW_QOS : 4; /* 11:8 */
    unsigned  UNUSED1 : 20; /* 31:12 */
} _icp_icp_sierra_a5_csr_acess;

typedef union{
    _icp_icp_sierra_a5_csr_acess bitfields,bits;
    unsigned int u32All;

} ICP_ICP_SIERRA_A5_CSR_ACESS;

typedef struct{
    unsigned  GP_REG : 32; /* 31:0 */
} _icp_icp_sierra_a5_csr_ca5_gp_0_reg;

typedef union{
    _icp_icp_sierra_a5_csr_ca5_gp_0_reg bitfields,bits;
    unsigned int u32All;

} ICP_ICP_SIERRA_A5_CSR_CA5_GP_0_REG;

typedef struct{
    unsigned  GP_REG : 32; /* 31:0 */
} _icp_icp_sierra_a5_csr_ca5_gp_1_reg;

typedef union{
    _icp_icp_sierra_a5_csr_ca5_gp_1_reg bitfields,bits;
    unsigned int u32All;

} ICP_ICP_SIERRA_A5_CSR_CA5_GP_1_REG;

typedef struct{
    unsigned  GP_REG : 32; /* 31:0 */
} _icp_icp_sierra_a5_csr_ca5_gp_2_reg;

typedef union{
    _icp_icp_sierra_a5_csr_ca5_gp_2_reg bitfields,bits;
    unsigned int u32All;

} ICP_ICP_SIERRA_A5_CSR_CA5_GP_2_REG;

typedef struct{
    unsigned  GP_REG : 32; /* 31:0 */
} _icp_icp_sierra_a5_csr_ca5_gp_3_reg;

typedef union{
    _icp_icp_sierra_a5_csr_ca5_gp_3_reg bitfields,bits;
    unsigned int u32All;

} ICP_ICP_SIERRA_A5_CSR_CA5_GP_3_REG;

typedef struct{
    unsigned  GP_REG : 32; /* 31:0 */
} _icp_icp_sierra_a5_csr_ca5_gp_4_reg;

typedef union{
    _icp_icp_sierra_a5_csr_ca5_gp_4_reg bitfields,bits;
    unsigned int u32All;

} ICP_ICP_SIERRA_A5_CSR_CA5_GP_4_REG;

typedef struct{
    unsigned  GP_REG : 32; /* 31:0 */
} _icp_icp_sierra_a5_csr_ca5_gp_5_reg;

typedef union{
    _icp_icp_sierra_a5_csr_ca5_gp_5_reg bitfields,bits;
    unsigned int u32All;

} ICP_ICP_SIERRA_A5_CSR_CA5_GP_5_REG;

typedef struct{
    unsigned  GP_REG : 32; /* 31:0 */
} _icp_icp_sierra_a5_csr_ca5_gp_6_reg;

typedef union{
    _icp_icp_sierra_a5_csr_ca5_gp_6_reg bitfields,bits;
    unsigned int u32All;

} ICP_ICP_SIERRA_A5_CSR_CA5_GP_6_REG;

typedef struct{
    unsigned  GP_REG : 32; /* 31:0 */
} _icp_icp_sierra_a5_csr_ca5_gp_7_reg;

typedef union{
    _icp_icp_sierra_a5_csr_ca5_gp_7_reg bitfields,bits;
    unsigned int u32All;

} ICP_ICP_SIERRA_A5_CSR_CA5_GP_7_REG;

typedef struct{
    unsigned  GP_REG : 32; /* 31:0 */
} _icp_icp_sierra_a5_csr_ca5_gp_8_reg;

typedef union{
    _icp_icp_sierra_a5_csr_ca5_gp_8_reg bitfields,bits;
    unsigned int u32All;

} ICP_ICP_SIERRA_A5_CSR_CA5_GP_8_REG;

typedef struct{
    unsigned  GP_REG : 32; /* 31:0 */
} _icp_icp_sierra_a5_csr_ca5_gp_9_reg;

typedef union{
    _icp_icp_sierra_a5_csr_ca5_gp_9_reg bitfields,bits;
    unsigned int u32All;

} ICP_ICP_SIERRA_A5_CSR_CA5_GP_9_REG;

typedef struct{
    unsigned  GP_REG : 32; /* 31:0 */
} _icp_icp_sierra_a5_csr_ca5_gp_10_reg;

typedef union{
    _icp_icp_sierra_a5_csr_ca5_gp_10_reg bitfields,bits;
    unsigned int u32All;

} ICP_ICP_SIERRA_A5_CSR_CA5_GP_10_REG;

typedef struct{
    unsigned  GP_REG : 32; /* 31:0 */
} _icp_icp_sierra_a5_csr_ca5_gp_11_reg;

typedef union{
    _icp_icp_sierra_a5_csr_ca5_gp_11_reg bitfields,bits;
    unsigned int u32All;

} ICP_ICP_SIERRA_A5_CSR_CA5_GP_11_REG;

typedef struct{
    unsigned  GP_REG : 32; /* 31:0 */
} _icp_icp_sierra_a5_csr_ca5_gp_12_reg;

typedef union{
    _icp_icp_sierra_a5_csr_ca5_gp_12_reg bitfields,bits;
    unsigned int u32All;

} ICP_ICP_SIERRA_A5_CSR_CA5_GP_12_REG;

typedef struct{
    unsigned  GP_REG : 32; /* 31:0 */
} _icp_icp_sierra_a5_csr_ca5_gp_13_reg;

typedef union{
    _icp_icp_sierra_a5_csr_ca5_gp_13_reg bitfields,bits;
    unsigned int u32All;

} ICP_ICP_SIERRA_A5_CSR_CA5_GP_13_REG;

typedef struct{
    unsigned  GP_REG : 32; /* 31:0 */
} _icp_icp_sierra_a5_csr_ca5_gp_14_reg;

typedef union{
    _icp_icp_sierra_a5_csr_ca5_gp_14_reg bitfields,bits;
    unsigned int u32All;

} ICP_ICP_SIERRA_A5_CSR_CA5_GP_14_REG;

typedef struct{
    unsigned  GP_REG : 32; /* 31:0 */
} _icp_icp_sierra_a5_csr_ca5_gp_15_reg;

typedef union{
    _icp_icp_sierra_a5_csr_ca5_gp_15_reg bitfields,bits;
    unsigned int u32All;

} ICP_ICP_SIERRA_A5_CSR_CA5_GP_15_REG;

typedef struct{
    unsigned  GP_REG : 32; /* 31:0 */
} _icp_icp_sierra_a5_csr_ca5_gp_16_reg;

typedef union{
    _icp_icp_sierra_a5_csr_ca5_gp_16_reg bitfields,bits;
    unsigned int u32All;

} ICP_ICP_SIERRA_A5_CSR_CA5_GP_16_REG;

typedef struct{
    unsigned  GP_REG : 32; /* 31:0 */
} _icp_icp_sierra_a5_csr_ca5_gp_17_reg;

typedef union{
    _icp_icp_sierra_a5_csr_ca5_gp_17_reg bitfields,bits;
    unsigned int u32All;

} ICP_ICP_SIERRA_A5_CSR_CA5_GP_17_REG;

typedef struct{
    unsigned  GP_REG : 32; /* 31:0 */
} _icp_icp_sierra_a5_csr_ca5_gp_18_reg;

typedef union{
    _icp_icp_sierra_a5_csr_ca5_gp_18_reg bitfields,bits;
    unsigned int u32All;

} ICP_ICP_SIERRA_A5_CSR_CA5_GP_18_REG;

typedef struct{
    unsigned  GP_REG : 32; /* 31:0 */
} _icp_icp_sierra_a5_csr_ca5_gp_19_reg;

typedef union{
    _icp_icp_sierra_a5_csr_ca5_gp_19_reg bitfields,bits;
    unsigned int u32All;

} ICP_ICP_SIERRA_A5_CSR_CA5_GP_19_REG;

typedef struct{
    unsigned  UNUSED0 : 7; /* 6:0 */
    unsigned  CSR_A5_STANDBYWFI : 1; /* 7:7 */
    unsigned  CSR_A5_STANDBYWFE : 1; /* 8:8 */
    unsigned  CSR_A5_CLK_STATUS : 1; /* 9:9 */
    unsigned  UNUSED1 : 22; /* 31:10 */
} _icp_icp_sierra_a5_csr_a5_status;

typedef union{
    _icp_icp_sierra_a5_csr_a5_status bitfields,bits;
    unsigned int u32All;

} ICP_ICP_SIERRA_A5_CSR_A5_STATUS;

typedef struct{
    unsigned  CFG_LM_MID : 7; /* 6:0 */
    unsigned  UNUSED0 : 1; /* 7:7 */
    unsigned  CFG_LM_PID : 4; /* 11:8 */
    unsigned  UNUSED1 : 4; /* 15:12 */
    unsigned  CFG_LM_BID : 3; /* 18:16 */
    unsigned  UNUSED2 : 13; /* 31:19 */
} _icp_icp_sierra_a5_qgic2_lm_id;

typedef union{
    _icp_icp_sierra_a5_qgic2_lm_id bitfields,bits;
    unsigned int u32All;

} ICP_ICP_SIERRA_A5_QGIC2_LM_ID;

typedef struct{
    unsigned  SPARE : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _icp_icp_sierra_a5_spare;

typedef union{
    _icp_icp_sierra_a5_spare bitfields,bits;
    unsigned int u32All;

} ICP_ICP_SIERRA_A5_SPARE;

typedef struct{
    unsigned  STEP : 8; /* 7:0 */
    unsigned  TIER : 8; /* 15:8 */
    unsigned  GENERATION : 8; /* 23:16 */
    unsigned  UNUSED0 : 8; /* 31:24 */
} _icp_icp_csr_titan_version;

typedef union{
    _icp_icp_csr_titan_version bitfields,bits;
    unsigned int u32All;

} ICP_ICP_CSR_TITAN_VERSION;

typedef struct{
    unsigned  STEP : 16; /* 15:0 */
    unsigned  MINOR : 12; /* 27:16 */
    unsigned  MAJOR : 4; /* 31:28 */
} _icp_icp_csr_hw_version;

typedef union{
    _icp_icp_csr_hw_version bitfields,bits;
    unsigned int u32All;

} ICP_ICP_CSR_HW_VERSION;

typedef struct{
    unsigned  SPARE : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _icp_icp_csr_spare;

typedef union{
    _icp_icp_csr_spare bitfields,bits;
    unsigned int u32All;

} ICP_ICP_CSR_SPARE;

/*----------------------------------------------------------------------
        ENUM Data Structures
----------------------------------------------------------------------*/

typedef enum{
    ICP_ICP_QGIC2_GICD_CTLR_ENABLE_CLR  = 0x0,
    ICP_ICP_QGIC2_GICD_CTLR_ENABLE_SET  = 0x1
} ICP_ICP_QGIC2_GICD_CTLR_ENABLE_ENUM;


typedef enum{
    ICP_ICP_QGIC2_GICD_CTLR_ENABLE_NS_CLR  = 0x0,
    ICP_ICP_QGIC2_GICD_CTLR_ENABLE_NS_SET  = 0x1
} ICP_ICP_QGIC2_GICD_CTLR_ENABLE_NS_ENUM;


typedef enum{
    ICP_ICP_QGIC2_GICD_ANSACR_GICD_CGCR_SEC  = 0x0,
    ICP_ICP_QGIC2_GICD_ANSACR_GICD_CGCR_NS  = 0x1
} ICP_ICP_QGIC2_GICD_ANSACR_GICD_CGCR_ENUM;


typedef enum{
    ICP_ICP_QGIC2_GICD_CGCR_DI_RD_ENABLE  = 0x0,
    ICP_ICP_QGIC2_GICD_CGCR_DI_RD_DISABLE  = 0x1
} ICP_ICP_QGIC2_GICD_CGCR_DI_RD_ENUM;


typedef enum{
    ICP_ICP_QGIC2_GICD_CGCR_DI_DEMET_ENABLE  = 0x0,
    ICP_ICP_QGIC2_GICD_CGCR_DI_DEMET_DISABLE  = 0x1
} ICP_ICP_QGIC2_GICD_CGCR_DI_DEMET_ENUM;


typedef enum{
    ICP_ICP_QGIC2_GICD_CGCR_DI_PPI_SPI_STATE_ENABLE  = 0x0,
    ICP_ICP_QGIC2_GICD_CGCR_DI_PPI_SPI_STATE_DISABLE  = 0x1
} ICP_ICP_QGIC2_GICD_CGCR_DI_PPI_SPI_STATE_ENUM;


typedef enum{
    ICP_ICP_QGIC2_GICD_CGCR_DI_SGI_STATE_ENABLE  = 0x0,
    ICP_ICP_QGIC2_GICD_CGCR_DI_SGI_STATE_DISABLE  = 0x1
} ICP_ICP_QGIC2_GICD_CGCR_DI_SGI_STATE_ENUM;


typedef enum{
    ICP_ICP_QGIC2_GICD_CGCR_TOP_ENABLE  = 0x0,
    ICP_ICP_QGIC2_GICD_CGCR_TOP_DISABLE  = 0x1
} ICP_ICP_QGIC2_GICD_CGCR_TOP_ENUM;


typedef enum{
    ICP_ICP_QGIC2_GICD_SGIR_SATT_SECURE  = 0x0,
    ICP_ICP_QGIC2_GICD_SGIR_SATT_NONSECURE  = 0x1
} ICP_ICP_QGIC2_GICD_SGIR_SATT_ENUM;


typedef enum{
    ICP_ICP_QGIC2_GICD_SGIR_T_LIST_CPU0  = 0x1,
    ICP_ICP_QGIC2_GICD_SGIR_T_LIST_CPU1  = 0x2,
    ICP_ICP_QGIC2_GICD_SGIR_T_LIST_CPU2  = 0x4,
    ICP_ICP_QGIC2_GICD_SGIR_T_LIST_CPU3  = 0x8,
    ICP_ICP_QGIC2_GICD_SGIR_T_LIST_CPU4  = 0x10,
    ICP_ICP_QGIC2_GICD_SGIR_T_LIST_CPU5  = 0x20,
    ICP_ICP_QGIC2_GICD_SGIR_T_LIST_CPU6  = 0x40,
    ICP_ICP_QGIC2_GICD_SGIR_T_LIST_CPU7  = 0x80
} ICP_ICP_QGIC2_GICD_SGIR_T_LIST_ENUM;


typedef enum{
    ICP_ICP_QGIC2_GICD_SGIR_T_FILTER_LIST  = 0x0,
    ICP_ICP_QGIC2_GICD_SGIR_T_FILTER_OTHERS  = 0x1,
    ICP_ICP_QGIC2_GICD_SGIR_T_FILTER_MID  = 0x2,
    ICP_ICP_QGIC2_GICD_SGIR_T_FILTER_NA  = 0x3
} ICP_ICP_QGIC2_GICD_SGIR_T_FILTER_ENUM;


typedef enum{
    ICP_ICP_QGIC2_GICH_HCR_EN_CLR  = 0x0,
    ICP_ICP_QGIC2_GICH_HCR_EN_SET  = 0x1
} ICP_ICP_QGIC2_GICH_HCR_EN_ENUM;


typedef enum{
    ICP_ICP_QGIC2_GICH_HCR_UIE_CLR  = 0x0,
    ICP_ICP_QGIC2_GICH_HCR_UIE_SET  = 0x1
} ICP_ICP_QGIC2_GICH_HCR_UIE_ENUM;


typedef enum{
    ICP_ICP_QGIC2_GICH_HCR_SKIDIE_CLR  = 0x0,
    ICP_ICP_QGIC2_GICH_HCR_SKIDIE_SET  = 0x1
} ICP_ICP_QGIC2_GICH_HCR_SKIDIE_ENUM;


typedef enum{
    ICP_ICP_QGIC2_GICH_HCR_NPIE_CLR  = 0x0,
    ICP_ICP_QGIC2_GICH_HCR_NPIE_SET  = 0x1
} ICP_ICP_QGIC2_GICH_HCR_NPIE_ENUM;


typedef enum{
    ICP_ICP_QGIC2_GICH_HCR_VEG0IE_CLR  = 0x0,
    ICP_ICP_QGIC2_GICH_HCR_VEG0IE_SET  = 0x1
} ICP_ICP_QGIC2_GICH_HCR_VEG0IE_ENUM;


typedef enum{
    ICP_ICP_QGIC2_GICH_HCR_VDG0IE_CLR  = 0x0,
    ICP_ICP_QGIC2_GICH_HCR_VDG0IE_SET  = 0x1
} ICP_ICP_QGIC2_GICH_HCR_VDG0IE_ENUM;


typedef enum{
    ICP_ICP_QGIC2_GICH_HCR_VEG1IE_CLR  = 0x0,
    ICP_ICP_QGIC2_GICH_HCR_VEG1IE_SET  = 0x1
} ICP_ICP_QGIC2_GICH_HCR_VEG1IE_ENUM;


typedef enum{
    ICP_ICP_QGIC2_GICH_HCR_VDG1IE_CLR  = 0x0,
    ICP_ICP_QGIC2_GICH_HCR_VDG1IE_SET  = 0x1
} ICP_ICP_QGIC2_GICH_HCR_VDG1IE_ENUM;


typedef enum{
    ICP_ICP_QGIC2_GICH_EISR_LR_NOT_EOI  = 0x0,
    ICP_ICP_QGIC2_GICH_EISR_LR_EOI  = 0x1
} ICP_ICP_QGIC2_GICH_EISR_LR_ENUM;


typedef enum{
    ICP_ICP_QGIC2_GICH_ELRSR_LR_NOT_EMPTY  = 0x0,
    ICP_ICP_QGIC2_GICH_ELRSR_LR_EMPTY  = 0x1
} ICP_ICP_QGIC2_GICH_ELRSR_LR_ENUM;


typedef enum{
    ICP_ICP_QGIC2_GICH_APR_PRI_INACTIVE  = 0x0,
    ICP_ICP_QGIC2_GICH_APR_PRI_ACTIVE  = 0x1
} ICP_ICP_QGIC2_GICH_APR_PRI_ENUM;


typedef enum{
    ICP_ICP_QGIC2_GICC_CTLR_ENABLE_CLR  = 0x0,
    ICP_ICP_QGIC2_GICC_CTLR_ENABLE_SET  = 0x1
} ICP_ICP_QGIC2_GICC_CTLR_ENABLE_ENUM;


typedef enum{
    ICP_ICP_QGIC2_GICC_CTLR_ENABLE_NS_CLR  = 0x0,
    ICP_ICP_QGIC2_GICC_CTLR_ENABLE_NS_SET  = 0x1
} ICP_ICP_QGIC2_GICC_CTLR_ENABLE_NS_ENUM;


typedef enum{
    ICP_ICP_QGIC2_GICC_CTLR_ACKCTL_DISABLE_ACK_OF_NS_PENDING  = 0x0,
    ICP_ICP_QGIC2_GICC_CTLR_ACKCTL_ENABLE_ACK_OF_NS_PENDING  = 0x1
} ICP_ICP_QGIC2_GICC_CTLR_ACKCTL_ENUM;


typedef enum{
    ICP_ICP_QGIC2_GICC_CTLR_S_DEST_IRQ  = 0x0,
    ICP_ICP_QGIC2_GICC_CTLR_S_DEST_FIQ  = 0x1
} ICP_ICP_QGIC2_GICC_CTLR_S_DEST_ENUM;


typedef enum{
    ICP_ICP_QGIC2_GICC_CTLR_SBPR_BANKED  = 0x0,
    ICP_ICP_QGIC2_GICC_CTLR_SBPR_RESTRICTED  = 0x1
} ICP_ICP_QGIC2_GICC_CTLR_SBPR_ENUM;


typedef enum{
    ICP_ICP_QGIC2_GICC_CTLR_FIQBYPDISABLE_CLR  = 0x0,
    ICP_ICP_QGIC2_GICC_CTLR_FIQBYPDISABLE_SET  = 0x1
} ICP_ICP_QGIC2_GICC_CTLR_FIQBYPDISABLE_ENUM;


typedef enum{
    ICP_ICP_QGIC2_GICC_CTLR_IRQBYPDISABLE_CLR  = 0x0,
    ICP_ICP_QGIC2_GICC_CTLR_IRQBYPDISABLE_SET  = 0x1
} ICP_ICP_QGIC2_GICC_CTLR_IRQBYPDISABLE_ENUM;


typedef enum{
    ICP_ICP_QGIC2_GICC_CTLR_EOIMODE_PD_AND_DI  = 0x0,
    ICP_ICP_QGIC2_GICC_CTLR_EOIMODE_PD  = 0x1
} ICP_ICP_QGIC2_GICC_CTLR_EOIMODE_ENUM;


typedef enum{
    ICP_ICP_QGIC2_GICC_APR_PRI_NA  = 0x0,
    ICP_ICP_QGIC2_GICC_APR_PRI_A  = 0x1
} ICP_ICP_QGIC2_GICC_APR_PRI_ENUM;


typedef enum{
    ICP_ICP_QGIC2_GICC_NSAPR_PRI_NA  = 0x0,
    ICP_ICP_QGIC2_GICC_NSAPR_PRI_A  = 0x1
} ICP_ICP_QGIC2_GICC_NSAPR_PRI_ENUM;


typedef enum{
    ICP_ICP_QGIC2_GICV_CTLR_ENABLE_G0_CLR  = 0x0,
    ICP_ICP_QGIC2_GICV_CTLR_ENABLE_G0_SET  = 0x1
} ICP_ICP_QGIC2_GICV_CTLR_ENABLE_G0_ENUM;


typedef enum{
    ICP_ICP_QGIC2_GICV_CTLR_ENABLE_G1_CLR  = 0x0,
    ICP_ICP_QGIC2_GICV_CTLR_ENABLE_G1_SET  = 0x1
} ICP_ICP_QGIC2_GICV_CTLR_ENABLE_G1_ENUM;


typedef enum{
    ICP_ICP_QGIC2_GICV_CTLR_ACKCTL_NO_IAR_4G0  = 0x0,
    ICP_ICP_QGIC2_GICV_CTLR_ACKCTL_IAR_4G0  = 0x1
} ICP_ICP_QGIC2_GICV_CTLR_ACKCTL_ENUM;


typedef enum{
    ICP_ICP_QGIC2_GICV_CTLR_FIQEN_IRQ  = 0x0,
    ICP_ICP_QGIC2_GICV_CTLR_FIQEN_FIQ  = 0x1
} ICP_ICP_QGIC2_GICV_CTLR_FIQEN_ENUM;


typedef enum{
    ICP_ICP_QGIC2_GICV_CTLR_GBPR_BANKED  = 0x0,
    ICP_ICP_QGIC2_GICV_CTLR_GBPR_G0  = 0x1
} ICP_ICP_QGIC2_GICV_CTLR_GBPR_ENUM;


typedef enum{
    ICP_ICP_QGIC2_GICV_CTLR_EOIMODE_PD_AND_DI  = 0x0,
    ICP_ICP_QGIC2_GICV_CTLR_EOIMODE_PD  = 0x1
} ICP_ICP_QGIC2_GICV_CTLR_EOIMODE_ENUM;


typedef enum{
    ICP_ICP_QGIC2_GICV_APR_PRI_NA  = 0x0,
    ICP_ICP_QGIC2_GICV_APR_PRI_A  = 0x1
} ICP_ICP_QGIC2_GICV_APR_PRI_ENUM;


typedef enum{
    ICP_ICP_QTMR_QTMR_AC_CNTNSAR_FG0_NSN_SECURE_ONLY  = 0x0,
    ICP_ICP_QTMR_QTMR_AC_CNTNSAR_FG0_NSN_SECURE_OR_NONSECURE  = 0x1
} ICP_ICP_QTMR_QTMR_AC_CNTNSAR_FG0_NSN_ENUM;


typedef enum{
    ICP_ICP_QTMR_QTMR_AC_CNTTIDR_FG0_F0_CFG_FI  = 0x0,
    ICP_ICP_QTMR_QTMR_AC_CNTTIDR_FG0_F0_CFG_FVI  = 0x1,
    ICP_ICP_QTMR_QTMR_AC_CNTTIDR_FG0_F0_CFG_FPLO  = 0x2,
    ICP_ICP_QTMR_QTMR_AC_CNTTIDR_FG0_F0_CFG_RSVD  = 0x3
} ICP_ICP_QTMR_QTMR_AC_CNTTIDR_FG0_F0_CFG_ENUM;


typedef enum{
    ICP_ICP_QTMR_QTMR_V1_CNTP_CTL_EN_DISABLED  = 0x0,
    ICP_ICP_QTMR_QTMR_V1_CNTP_CTL_EN_ENABLED  = 0x1
} ICP_ICP_QTMR_QTMR_V1_CNTP_CTL_EN_ENUM;


typedef enum{
    ICP_ICP_QTMR_QTMR_V1_CNTP_CTL_IMSK_UNMASK_INTERRUPT  = 0x0,
    ICP_ICP_QTMR_QTMR_V1_CNTP_CTL_IMSK_MASK_INTERRUPT  = 0x1
} ICP_ICP_QTMR_QTMR_V1_CNTP_CTL_IMSK_ENUM;


typedef enum{
    ICP_ICP_QTMR_QTMR_V1_CNTP_CTL_ISTAT_INTERRUPT_NOT_PENDING  = 0x0,
    ICP_ICP_QTMR_QTMR_V1_CNTP_CTL_ISTAT_INTERRUPT_PENDING  = 0x1
} ICP_ICP_QTMR_QTMR_V1_CNTP_CTL_ISTAT_ENUM;


typedef enum{
    ICP_ICP_QTMR_QTMR_V1_CNTV_CTL_EN_DISABLED  = 0x0,
    ICP_ICP_QTMR_QTMR_V1_CNTV_CTL_EN_ENABLED  = 0x1
} ICP_ICP_QTMR_QTMR_V1_CNTV_CTL_EN_ENUM;


typedef enum{
    ICP_ICP_QTMR_QTMR_V1_CNTV_CTL_IMSK_UNMASK_INTERRUPT  = 0x0,
    ICP_ICP_QTMR_QTMR_V1_CNTV_CTL_IMSK_MASK_INTERRUPT  = 0x1
} ICP_ICP_QTMR_QTMR_V1_CNTV_CTL_IMSK_ENUM;


typedef enum{
    ICP_ICP_QTMR_QTMR_V1_CNTV_CTL_ISTAT_INTERRUPT_NOT_PENDING  = 0x0,
    ICP_ICP_QTMR_QTMR_V1_CNTV_CTL_ISTAT_INTERRUPT_PENDING  = 0x1
} ICP_ICP_QTMR_QTMR_V1_CNTV_CTL_ISTAT_ENUM;


typedef enum{
    ICP_ICP_QTMR_QTMR_V2_CNTP_CTL_EN_DISABLED  = 0x0,
    ICP_ICP_QTMR_QTMR_V2_CNTP_CTL_EN_ENABLED  = 0x1
} ICP_ICP_QTMR_QTMR_V2_CNTP_CTL_EN_ENUM;


typedef enum{
    ICP_ICP_QTMR_QTMR_V2_CNTP_CTL_IMSK_UNMASK_INTERRUPT  = 0x0,
    ICP_ICP_QTMR_QTMR_V2_CNTP_CTL_IMSK_MASK_INTERRUPT  = 0x1
} ICP_ICP_QTMR_QTMR_V2_CNTP_CTL_IMSK_ENUM;


typedef enum{
    ICP_ICP_QTMR_QTMR_V2_CNTP_CTL_ISTAT_INTERRUPT_NOT_PENDING  = 0x0,
    ICP_ICP_QTMR_QTMR_V2_CNTP_CTL_ISTAT_INTERRUPT_PENDING  = 0x1
} ICP_ICP_QTMR_QTMR_V2_CNTP_CTL_ISTAT_ENUM;


typedef enum{
    ICP_ICP_QTMR_QTMR_V2_CNTV_CTL_EN_DISABLED  = 0x0,
    ICP_ICP_QTMR_QTMR_V2_CNTV_CTL_EN_ENABLED  = 0x1
} ICP_ICP_QTMR_QTMR_V2_CNTV_CTL_EN_ENUM;


typedef enum{
    ICP_ICP_QTMR_QTMR_V2_CNTV_CTL_IMSK_UNMASK_INTERRUPT  = 0x0,
    ICP_ICP_QTMR_QTMR_V2_CNTV_CTL_IMSK_MASK_INTERRUPT  = 0x1
} ICP_ICP_QTMR_QTMR_V2_CNTV_CTL_IMSK_ENUM;


typedef enum{
    ICP_ICP_QTMR_QTMR_V2_CNTV_CTL_ISTAT_INTERRUPT_NOT_PENDING  = 0x0,
    ICP_ICP_QTMR_QTMR_V2_CNTV_CTL_ISTAT_INTERRUPT_PENDING  = 0x1
} ICP_ICP_QTMR_QTMR_V2_CNTV_CTL_ISTAT_ENUM;

#endif // TITAN170_ICP_H
